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10 April 2024 Innovations in design of backend interconnect short loop test chips for faster process and yield development
Dipto Thakurta
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Proceedings Volume PC12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII; (2024) https://doi.org/10.1117/12.3012302
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States
Abstract
The talk will focus on back end short loop test chip design innovations jointly developed by Design Enablement and Process Technology Development teams at Intel. These short loop test chips serve as quick turn monitors and help to decouple frontend and backend process and yield development. The test chip design innovations, some using ML/AI techniques, allow fast sort testing for design rule coverage, product like layouts, known layout defect modes and litho hot spots. These test chips are designed with FA/FI features for fast debug and for driving process/yield development to low defect density (DD) regimes.
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Dipto Thakurta "Innovations in design of backend interconnect short loop test chips for faster process and yield development", Proc. SPIE PC12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, (10 April 2024); https://doi.org/10.1117/12.3012302
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KEYWORDS
Design and modelling
Design rules
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