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10 April 2024 Opportunities and challenges in advanced logic scaling using monolithic 3D integration
Marko Radosavljevic
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Proceedings Volume PC12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII; (2024) https://doi.org/10.1117/12.3012337
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States
Abstract
Transistor scaling has been one of the key engines driving Moore's Law and our semiconductor industry. To maintain this pace of scaling, many new architectural changes have been proposed, and introduced since the start of this century, such as FinFETs and gate-all-around (GAA). Many researchers agree that the next architecture change will go further in 3D by stacking transistors in what is called complementary FET or CFET. In this presentation, we will discuss benefits that CFET may provide, some CFET implementations as well as latest experimental demonstrations of CFET architectures. Specifically, we will highlight the opportunities and challenges in vertical patterning and aspect ratios required for what is referred to as self-aligned CFET. These include vertically stacked dual epi source-drain, vertically stacked dual metal gate workfunctions as well as backside interconnects. We will use recent progress in these technologies to experimentally demonstrate simple circuits in CFET architecture.
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Marko Radosavljevic "Opportunities and challenges in advanced logic scaling using monolithic 3D integration", Proc. SPIE PC12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, (10 April 2024); https://doi.org/10.1117/12.3012337
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KEYWORDS
Transistors
Logic
Gallium arsenide
Germanium
Industry
Metals
Moores law
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