Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems

Chun-Chang Yu; Pei-Chun Lin; Yi-Chang Lu; Charlie Chung-Ping Chen

doi:10.1117/1.JMM.17.3.031202

22 August 2018 Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems

Chun-Chang Yu, Pei-Chun Lin, Yi-Chang Lu, Charlie Chung-Ping Chen

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 17, Issue 3, 031202 (August 2018). https://doi.org/10.1117/1.JMM.17.3.031202

Abstract

Data throughput is a critical metric in a multiple electron-beam direct-write (MEBDW) system so that heavy-duty data processing equipment is required. The main challenge is about how to achieve high performance with cost-effective techniques. We propose a high compression rate algorithm for efficient data transfer and high speed decompression hardware to raise data throughput of the system. The hardware decoder uses pipeline architecture, a run-length encoding first-in-first-out queue, and parallel dispatch logic to increase the throughput. The decoder is evaluated on field-programmable gate array and simulated with layout images that are compressed using the proposed compression software. The results demonstrate 18.2% better compression rate and 254.8% better throughput than the previous work with similar hardware cost. Because no static random-access memory is used in the design, the channel numbers of the system can be easily scaled up, which makes it possible for the next-generation MEBDW system to achieve higher wafer per hour targets.

Citation Download Citation

Chun-Chang Yu, Pei-Chun Lin, Yi-Chang Lu, and Charlie Chung-Ping Chen "Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems," Journal of Micro/Nanolithography, MEMS, and MOEMS 17(3), 031202 (22 August 2018). https://doi.org/10.1117/1.JMM.17.3.031202

Received: 14 February 2018; Accepted: 24 May 2018; Published: 22 August 2018

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