During the past few years, the per-chip count of processing cores has increased with the emergence of the multi/many core era to meet the high-performance requirements of on-chip processing cores. However, requirements for larger bandwidth in multi/many processors cannot be fulfilled employing traditional electrical on-chip interconnections. Optical on-chip interconnects provide a substitute to resolve this issue for high-performance computing. Optical routers/switches are one of the key components, which determine the cost and performance of optical networks-on-chip, to realize on-chip communication among cores. We present an optimized design of 5  ×  5 nonblocking optical router using silicon microring-based 2  ×  2 switching elements called as SMOR. The proposed five-port SMOR optical router is constructed using 10 switching elements in unoptimized design, which is further reduced to 8 switching elements via available optimization scheme. Detailed performance analysis of proposed five-port optical router in terms of cross-talk noise, insertion loss, and power consumption is furnished and discussed. In comparison to existing architectures of optical router/switches of same scale, proposed SMOR has achieved up to 68% minimization in a number of switching elements.