The use of III-V and group IV compounds in the same heterostructure is of great interest for high performances solar cells under concentration. In fact, the combination of these III-V and group IV compounds can lead to interesting strategic bandgap choices and engineering to better match the absorption of the solar spectrum, and therefore better solar cell performance. The series-connected quad-junctions (4J) solar cell strategies have the potential to improve solar cells performance and therefore enable low-cost concentrator photovoltaic (CPV) systems, allowing lower levelized cost of electricity (LCOE) from a CPV system. This work presents the investigation of the performance of dual junction (2J) GaInP/GaAs that might be implemented as upper cells with group IV (SiGeSn) cells as bottom cells. The aim of this study is to validate the epitaxial structure and the fabrication process for future 4J cells development. Pitch is varied from 125 μm to 400 μm for two different size of cells, in order to optimize solar cells performance under concentration (X) In the range of 100X to 1000X. Solar cells demonstrated high fill factor (FF) values and ideality factors (n) approaching unity per subcell have been obtained in the range of 100X to 500X. A FF of 85% and 88% are obtained at a concentration of 1000X for the bigger and smaller cells respectively, for the narrowest pitch. These results close to the state-of-the-art are encouraging for the implementation of this 2J with IV bottom subcell for the purpose of high performance 4J.
KEYWORDS: Silicon, Germanium, Interfaces, Multijunction solar cells, Photovoltaics, Electrochemical etching, Transmission electron microscopy, Chemical mechanical planarization, Solar cells
III-V solar cell cost reduction and direct III-V/Si integration can both be realized by depositing a thin layer of high-quality Ge on relatively low-cost Si substrates. However, direct epitaxial growth of Ge on Si substrates is difficult due to the 4% lattice mismatch between the film and the substrate. Threading dislocations (TDs) introduced within the Ge layer have a detrimental effect on device performances. The goal of this research is to address the perennial need to minimize the defect density of Ge epilayers grown on a Si substrate. We seek to accommodate the effects of the lattice mismatch by introducing a porous Si interface layer to intercept dislocations and prevent them from reaching the active layers of the device. The porous Si layer is formed through dislocation-selective electrochemical deep etching and thermal annealing. The porous layer created beneath the top Ge layer can both act as dislocation traps and as a soft compliant substrate, which displays high flexibility. Transmission electron microscopy (TEM) analysis of the Ge/porous Si interface shows that the lattice mismatch strain of the Ge films was almost relaxed. The surface roughness of this modified Ge/Si substrate has been reduced using chemical mechanical polishing (CMP) process to fulfil the requirements for epitaxy of III-V alloys. Finally, we present simulation results exploring the effect of threading dislocations on device performance.
Four-junction solar cells for space and terrestrial applications require a junction with a band gap of ∼1 eV for optimal performance. InGaAsN or InGaAsN(Sb) dilute nitride junctions have been demonstrated for this purpose, but in achieving the 14 mA/cm2 short-circuit current needed to match typical GaInP and GaAs junctions, the open-circuit voltage (VOC) and fill factor of these junctions are compromised. In multijunction devices incorporating materials with short diffusion lengths, we study the use of thin junctions to minimize sensitivity to varying material quality and ensure adequate transmission into lower junctions. An n-i-p device with 0.65-μm absorber thickness has sufficient short-circuit current, however, it relies less heavily on field-aided collection than a device with a 1-μm absorber. Our standard cell fabrication process, which includes a rapid thermal anneal of the contacts, yields a significant improvement in diffusion length and device performance. By optimizing a four-junction cell around a smaller 1-sun short-circuit current of 12.5 mA/cm2, we produced an InGaAsN(Sb) junction with open-circuit voltage of 0.44 V at 1000 suns (1 sun=100 mW/cm2), diode ideality factor of 1.4, and sufficient light transmission to allow >12.5 mA/cm2 in all four subcells.
Conference Committee Involvement (5)
Physics, Simulation, and Photonic Engineering of Photovoltaic Devices XIV
28 January 2025 | San Francisco, California, United States
Physics, Simulation, and Photonic Engineering of Photovoltaic Devices XIII
29 January 2024 | San Francisco, California, United States
Physics, Simulation, and Photonic Engineering of Photovoltaic Devices XII
30 January 2023 | San Francisco, California, United States
Physics, Simulation, and Photonic Engineering of Photovoltaic Devices XI
26 January 2022 | San Francisco, California, United States
Physics, Simulation, and Photonic Engineering of Photovoltaic Devices X
6 March 2021 | Online Only, California, United States
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