Dr. Babak Mokaberi Profile

Dr. Babak Mokaberi

Principal Process Engineer at SAMSUNG Austin Semiconductor LLC

SPIE Involvement:

Author

Publications (4)

Proceedings Article | 13 March 2018 Presentation + Paper

Holistic metrology qualification extension and its application to characterize overlay targets with asymmetric effects

Olavio Dos Santos Ferreira, Reza Sadat Gousheh, Bart Visser, Kenrick Lie, Rachel Teuwen, Pavel Izikson, Grzegorz Grzela, Babak Mokaberi, Steve Zhou, Justin Smith, Danish Husain, Ram Mandoy, Raul Olvera

Proceedings Volume 10585, 105850T (2018) https://doi.org/10.1117/12.2297184

KEYWORDS: Lithography, Diffraction, Metrology, Optical lithography, Polarization, Etching, Semiconducting wafers, Overlay metrology, Diffraction gratings

Read Abstract +

Ever increasing need for tighter on-product overlay (OPO), as well as enhanced accuracy in overlay metrology and methodology, is driving semiconductor industry’s technologists to innovate new approaches to OPO measurements. In case of High Volume Manufacturing (HVM) fabs, it is often critical to strive for both accuracy and robustness. Robustness, in particular, can be challenging in metrology since overlay targets can be impacted by proximity of other structures next to the overlay target (asymmetric effects), as well as symmetric stack changes such as photoresist height variations. Both symmetric and asymmetric contributors have impact on robustness. Furthermore, tweaking or optimizing wafer processing parameters for maximum yield may have an adverse effect on physical target integrity. As a result, measuring and monitoring physical changes or process abnormalities/artefacts in terms of new Key Performance Indicators (KPIs) is crucial for the end goal of minimizing true in-die overlay of the integrated circuits (ICs). IC manufacturing fabs often relied on CD-SEM in the past to capture true in-die overlay. Due to destructive and intrusive nature of CD-SEMs on certain materials, it’s desirable to characterize asymmetry effects for overlay targets via inline KPIs utilizing YieldStar (YS) metrology tools. These KPIs can also be integrated as part of (μDBO) target evaluation and selection for final recipe flow. In this publication, the Holistic Metrology Qualification (HMQ) flow was extended to account for process induced (asymmetric) effects such as Grating Imbalance (GI) and Bottom Grating Asymmetry (BGA). Local GI typically contributes to the intrafield OPO whereas BGA typically impacts the interfield OPO, predominantly at the wafer edge. Stack height variations highly impact overlay metrology accuracy, in particular in case of multi-layer LithoEtch Litho-Etch (LELE) overlay control scheme. Introducing a GI impact on overlay (in nm) KPI check quantifies the grating imbalance impact on overlay, whereas optimizing for accuracy using self-reference captures the bottom grating asymmetry effect. Measuring BGA after each process step before exposure of the top grating helps to identify which specific step introduces the asymmetry in the bottom grating. By evaluating this set of KPI's to a BEOL LELE overlay scheme, we can enhance robustness of recipe selection and target selection. Furthermore, these KPIs can be utilized to highlight process and equipment abnormalities. In this work, we also quantified OPO results with a self-contained methodology called Triangle Method. This method can be utilized for LELE layers with a common target and reference. This allows validating general μDBO accuracy, hence reducing the need for CD-SEM verification.

Proceedings Article | 28 March 2017 Presentation + Paper

A hybrid solution using computational prediction and measured data to accurately determine process corrections with reduced overlay sampling

Ben Noyes, Babak Mokaberi, Ram Mandoy, Alex Pate, Ralph Huijgen, Mike McBurney, Owen Chen

Proceedings Volume 10145, 1014508 (2017) https://doi.org/10.1117/12.2257486

KEYWORDS: Semiconductors, Modeling, Metrology, Data modeling, Computing systems, Control systems, Time metrology, Process control, Semiconducting wafers, Overlay metrology

Read Abstract +

Proceedings Article | 8 March 2016 Paper

Reducing overlay sampling for APC-based correction per exposure by replacing measured data with computational prediction

Ben Noyes, Babak Mokaberi, Jong Hun Oh, Hyun Sik Kim, Jun Ha Sung, Marc Kea

Proceedings Volume 9778, 977832 (2016) https://doi.org/10.1117/12.2219241

KEYWORDS: Semiconductors, Lithography, Metrology, Lithium, Data modeling, Computing systems, Time metrology, Semiconducting wafers, Systems modeling, Overlay metrology

Read Abstract +

Proceedings Article | 8 March 2016 Paper

Applications of on-product diffraction-based focus metrology in logic high volume manufacturing

Ben Noyes, Babak Mokaberi, David Bolton, Chen Li, Ashwin Palande, Kevin Park, Marc Noot, Marc Kea

Proceedings Volume 9778, 97782V (2016) https://doi.org/10.1117/12.2219303

KEYWORDS: Target detection, Metrology, Logic, Scanners, Time metrology, Finite element methods, High volume manufacturing, Critical dimension metrology, Semiconducting wafers, Yield improvement

Read Abstract +

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years