Mr. Barry Saville Profile

Barry Saville

at KLA New York

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Author

Publications (6)

Proceedings Article | 22 February 2021 Presentation + Paper

The emergence of inline screening for high volume manufacturing

Oreste Donzella, John Robinson, Kara Sherman, Justin Lach, Mike von den Hoff, Barry Saville, Thomas Groos, Alex Lim, David Price, Jay Rathert, Chet Lenox

Proceedings Volume 11611, 1161107 (2021) https://doi.org/10.1117/12.2584770

KEYWORDS: Semiconducting wafers, Reliability, Inspection, Process control, Semiconductors, Manufacturing, Packaging, Machine learning, Silicon carbide, High volume manufacturing

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Proceedings Article | 26 March 2019 Paper

Defect learning with predictive sampling for process improvement

Ian Tolle, Julie Lee, Dave Salvador, Barry Saville, Poh-Boon Yong, Gino Marcuccilli

Proceedings Volume 10959, 1095930 (2019) https://doi.org/10.1117/12.2523963

KEYWORDS: Yield improvement, Defect inspection, Machine learning, Semiconducting wafers, Data modeling, Optical inspection, Modulation, Inspection, Analytics

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SPIE Journal Paper | 5 September 2018

Defect detection strategies and process partitioning for single-expose EUV patterning

Luciana Meli, Karen Petrillo, Anuja De Silva, John Arnold, Nelson Felix, Chris Robinson, Benjamin Briggs, Shravan Matham, Yann Mignot, Jeffrey Shearer, Bassem Hamieh, Koichi Hontake, Lior Huli, Corey Lemley, Dave Hetzer, Eric Liu, Ko Akiteru, Shinichiro Kawakami, Takeshi Shimoaoki, Yusaku Hashimoto, Hiroshi Ichinomiya, Akiko Kai, Koichiro Tanaka, Ankit Jain, Heungsoo Choi, Barry Saville, Chet Lenox

JM3, Vol. 18, Issue 01, 011006, (September 2018) https://doi.org/10.1117/12.10.1117/1.JMM.18.1.011006

KEYWORDS: Inspection, Semiconducting wafers, Stochastic processes, Extreme ultraviolet, Etching, Defect detection, Electron beam lithography, Modulation, Coating, Extreme ultraviolet lithography

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Proceedings Article | 28 March 2018 Presentation + Paper

Defect detection strategies and process partitioning for SE EUV patterning

Proceedings Volume 10583, 105830E (2018) https://doi.org/10.1117/12.2297362

KEYWORDS: Inspection, Semiconducting wafers, Etching, Stochastic processes, Extreme ultraviolet, Modulation, Defect detection, Extreme ultraviolet lithography, Coating, Electron beam lithography

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Proceedings Article | 17 October 2008 Paper

Crystal growth printability in an advanced foundry FAB: a correlation study between STARlight and ultra broadband BrightField inspection technologies

Teng Hwee Ng, Mohammed Fahmy bin Rahmat, Barry Saville, Patrick Pak, WeeTeck Chia, Aaron Chin, Mike VanRiet, Russell Dover, Raj Badoni

Proceedings Volume 7122, 712213 (2008) https://doi.org/10.1117/12.801868

KEYWORDS: Inspection, Reticles, Semiconducting wafers, Printing, Scanning electron microscopy, Defect detection, Crystals, Crystallography, Defect inspection, Contamination

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Proceedings Article | 5 April 2007 Paper

Developing micro ADI methodology for new litho process monitoring strategies

Iris Mäge, Uwe Seifert, Barry Saville, Martin Tuckermann

Proceedings Volume 6518, 65180Q (2007) https://doi.org/10.1117/12.711416

KEYWORDS: Inspection, Semiconducting wafers, Wafer testing, Lithography, Photomasks, Wafer inspection, Etching, Defect inspection, Coating, Signal to noise ratio

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With the introduction of sub-100nm design rules, and especially 193nm photolithography, the development of new monitoring strategies is becoming increasingly important and necessary as new materials, new tools and new process challenges are introduced. Micro after-develop inspection (μADI) is a big step forward for photolithography defect monitoring as well as for integrated process learning. Resist quality and handling are essential for the whole process. The new 193nm resists exhibit an inherent defectivity, which is solely attributable to the quality of the resist. This defectivity comes from very small resist inhomogeneity, and leads to tiny bridging and stringer defects which can affect yield critically. Additionally, the entire lithography process (handling and scanning) is more critical, as process windows are decreasing to levels of common positioning accuracy and layer thicknesses. On the one hand, increased inspection sensitivity is needed to control the resist quality more tightly. With straightforward improvements to inspection technology, these sensitivity requirements can be met on test wafers, mainly because of the wafers' simplified structures and the absence of noise sources. However, on the other hand, there is a demand for a monitoring strategy which uses product wafers to enable the understanding of the interaction of material, structure, topography and shrinking process window. Test wafer monitoring is able to provide only an isolated snap shot of a specific work-step without further interaction. An integrated monitoring strategy of product wafers requires more advanced and innovative inspection technologies - providing both enhanced sensitivity and superior noise suppression - as lithography layers can show a lot of non-yield relevant etch mask defects that are very hard to suppress with common inspection techniques. This work introduces a novel after-lithography monitoring strategy based on a darkfield defect inspection technique on product wafers. Wafers can be scanned after development with superior noise suppression at resolutions approximating traditional brightfield inspection capabilities enabling lithography defect detection down to single line short levels. Thus, completely new inspection approaches for tool and line monitoring can be developed, sample plans can be optimized, and time to results and appropriate corrective actions can be significantly shortened.

Showing 5 of 6 publications

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