Overlay control is gaining more attention in recent years as technology moves into the 32nm era. Strict overlay
requirements are being driven not only by the process node but also the process techniques required to meet the design
requirements. Double patterning lithography and spacer pitch splitting techniques are driving innovative thinking with
respect to overlay control. As lithographers push the current capabilities of their 193nm immersion exposure tools they
are utilizing newly enabled control 'knobs'. 'Knobs' are defined as the adjustment points that add new degrees of
freedom for lithographers to control the scanner. Expanded control is required as current scanner capabilities are at best
marginal in meeting the performance requirements to support the ever demanding process nodes. This abstract is an
extension of the SPIE 2008 paper in which we performed thorough sources of variance analysis to provide insight as to
the benefits of utilizing high order scanner control knobs [1]. The extension this year is to expand the modeling
strategies and to validate the benefit through carefully designed experiments. The expanded modeling characterization
will explore not only high order correction capabilities but also characterize the use of field by field corrections as a
means to improve the overlay performance of the latest generation of immersion lithography tools. We will explore
various correction strategies for both grid and field modeling using KT AnalyzerTM.
The industry is facing a major challenge looking forward on the technology roadmap with respect to overlay control.
Immersion lithography has established itself as the POR for 45nm and for the next few nodes. As the gap closes between
scanner capability and device requirements new methodologies need to be taken into consideration. Double patterning
lithography is an approach that's being considered for 32 and below, but it creates very strict demands for overlay
performance. The fact that a single layer device will need to be patterned using two sequential single processes creates a
strong coupling between the 1st and 2nd exposure. The coupling effect during the double patterning process results in
extremely tight tolerances for overlay error and scanner capabilities.
The purpose of this paper is to explore a new modeling method to improve lithography performance for the 32nm node.
Not necessarily unique for double patterning, but as a general approach to improve overlay performance regardless of
which patterning process is implemented. We will achieve this by performing an in depth source of variance analysis of
current scanner performance and project the anticipated improvements from our new modeling approach. Since the new
modeling approach will involve 2nd and 3rd order corrections we will also provide and analysis that outlines current
metrology capabilities and sampling optimizations to further expand the opportunities of an efficient implementation of
such approach.
As Moore's Law drives CD smaller and smaller, overlay budget is shrinking rapidly. Furthermore, the cost of advanced
lithography tools prohibits usage of latest and greatest scanners on non-critical layers, resulting in different layers being
exposed with different tools; a practice commonly known as 'mix and match.' Since each tool has its unique signature,
mix and match becomes the source of high order overlay errors. Scanner alignment performance can be degraded by a
factor of 2 in mix and match, compared to single tool overlay operation. In a production environment where scanners
from different vendors are mixed, errors will be even more significant. Mix and match may also be applied to a single
scanner when multiple illumination modes are used to expose critical levels. This is because different illuminations will
have different impact to scanner aberration fingerprint. The semiconductor technology roadmap has reached a point
where such errors are no longer negligible.
Mix and match overlay errors consist of scanner stage grid component, scanner field distortion component, and process
induced wafer distortion. Scanner components are somewhat systematic, so they can be characterized on non product
wafers using a dedicated reticle. Since these components are known to drift over time it becomes necessary to monitor
them periodically, per scanner, per illumination.
In this paper, we outline a methodology for automating characterization of mix and match errors, and a control system
for real-time correction.
Optimal lithographic process control involves a closely coupled combination of test wafer and
product wafer characterization. It has been shown in previous work that MPX (Monitor Photo
Excursion) optical technology for line-end-shortening metrology of focus and dose provides reliable
and low cost product monitor solution. In this work we apply MPX technology to litho cell monitor
and control on test wafers. Focus-exposure matrix (FEM) wafers are measured and analyzed
automatically on a routine basis. Process window parameters are tracked over time by scanner,
including spatial analysis of results across the scanner field such as tilt and curvature.
Improvements in litho cell control are discussed.
Overlay accuracy is a key issue in semiconductor manufacturing process. In the ITRS roadmap also, overlay budgets are being reduced at a rapid pace. Coupled with the decreasing technology node budget allowances, alternative processing techniques are also driving overlay budgets to shrink. To meet those requirements, high order modeling of overlay error is potentially an effective solution. One source of overlay error is distortion matching between exposure tools. Matching can be broken down in to 2 areas; grid (stage related) and distortion (lens related). By using high order modeling of grid and distortion matching, we have been able to show overlay improvement of up to 50%. KLA-Tencor and Nikon are planning to provide automatic feedback system of high order compensation to exposure tool directly from metrology results. This feedback system can provide adjustment of coefficients of grid and distortion for periodical maintenance. Automating this process will lead to not only improved overlay control but also improved exposure tool productivity.
As device dimensions shrink the number of parameters influencing CD increases (PEB dispersion, development uniformity, resist thickness, BARC thickness, +/- scan focus control, scanner focus control at edge of the wafer...). Separation between all these contributors is not easy using only CD-SEM measurement, and particularly with isolated lines. For high volume manufacturing (where "time is money") and in the case of litho cluster drift, a quick and accurate diagnostic capability is an advantage for minimizing tool unavailability. An important attribute of this diagnostic capability is that its implementation is on standard production wafers. The use of production wafers enables continuous monitoring and also allows a direct correlation between monitoring measurements and the impact on product.
The technology that enables this type of diagnostic capability makes use of a compact dual tone line-end-shortening based target. A key benefit to this technology is that it provides a separation of the dose and focus parameters, which leads to quicker route cause determination.
After building a calibration model and determining minimum dose and focus sensitivity, both short term and long term stability of the model is investigated. The impact of wafer topology on model prediction is also investigated in order to assess on-product monitoring capability. The main error contributors are then identified for both track and scanner and the impact on CD control is evaluated. These cluster error contributors are then varied, first separately, and then combined. Measurement results are compared to the input parameters in order to determine error detection ability, measurement accuracy and separation capability.
CD control is one of the main parameters for IC product performances and a major contributor to yield performance. Traditional SEM metrology can be a challenge on particular layers due to normal process variation and has not proven to provide sufficient focus monitoring ability. This in turn causes false positives resulting in unnecessary rework, but more importantly missed focus excursions resulting in yield loss.
Alexander Starikov, Intel Corporation, alludes to the fact that focus and exposure "knobs" account for greater than 80% of CD correctible variance1. Spansion F25 is evaluating an alternative technology using an optical method for the indirect monitoring of the CD on the implant layer. The optical method utilizes a dual tone line-end-shortening (LES) target which is measured on a standard optical overlay tool. The dual tone technology enables the ability to separate the contributions of the focus and exposure resulting in a more accurate characterization of the two parameters on standard production wafers. Ultimately by keeping focus and exposure within acceptable limits it can be assumed that the CD will be within acceptable limits as well without the unnecessary rework caused by process variation.
By using designed experiments this paper will provide characterization of the LES technique on the implant layer showing its ability to separate focus-exposure errors vs. the traditional SEM metrology. Actual high volume production data will be used to compare the robustness and sensitivity of the two technologies in a real life production environment. An overall outline of the production implementation will be documented as well.
Due to the continuous shrinking of the design rules and, implicitly, of the lithographic process window, it becomes more and more important to implement a dynamic, on product, process monitoring and control based on both dose and focus parameters. The method we present targets lot-to-lot, inter-field and intra-field dose and focus effect monitoring and control. The advantage of simultaneous dose and focus control over the currently used CD correction by adjusting exposure dose only is visible in improvement of the CD distributions both at pre-etch and at post-etch phases. The 'On Product' monitoring and compensation is based on the optical measurement of a special compact line end shortening target which provides the unique ability to separate dose from focus on production wafers.
As design rules shrink and process windows become smaller, it is increasingly important to monitor exposure tool focus and exposure in order to maximize device yield. Economic considerations are forcing us to consider nearly all methods to improve yield across the wafer. For example, it is not uncommon in the industry that chips around the edge of the wafer have lower yield or device speed. These effects are typically due to process and exposure tool errors at the edge of the wafer. In order to improve yield and chip performance, we must characterize and correct for changes in the effective focus and exposure at the edge. Monitoring focus and exposure on product wafers is the most effective means for correction, since product wafers provide the most realistic view of exposure tool interactions with the process. In this work, on-product monitoring and correction is based on optical measurement using a compact line end shortening (LES) target that provides a unique separation of exposure and focus on product wafers. Our ultimate objective is indirect CD control, with maximum yield and little or no impact on productivity.
Parametric yield loss is an increasing fraction of total yield loss. Much of this originates in lithography in the form of pattern-limited yield. In particular, the ITRS has identified CD control at the 65nm technology node as a potential roadblock with no known solutions. At 65nm, shrinking design rules and narrowing process windows will become serious yield limiters. In high-volume production, corrections based on lot averages will have diminished correlation to device yield because APC systems will dramatically reduce error at the lot and wafer levels. As a result, cross-wafer and cross-field errors will dominate the systematic variation on 300mm wafers. Much of the yield loss will arise from hidden systematic variation, including intra-wafer dose and focus errors that occur during lithographic exposure. In addition, corollary systematic variation in the profiles of critical high-aspect-ratio structures will drive requirements for vertical process control. In this work, we model some of the potential yield losses and show how sensitive focus-exposure monitors and spectroscopic ellipsometry can be used to reduce the impact of hidden error on pattern limited yield, adding tens of millions of dollars in additional revenue per factory per year.
As the design rules shrink below 130nm it will become increasingly important to monitor and control focus and dose in-line, on product wafers to maintain the ever-decreasing process window. On process layers today, it is not uncommon to see focus related errors equaling between 50-100nm in magnitude. Today these errors go undetected and CD changes are typically corrected by making a dose correction to the exposure tool. However, corrections using dose can lead to significantly smaller process latitude and therefore, products out of spec. Using a technique that was first developed by Christopher Ausschnitt at IBM Microelectronics it is possible to monitor focus and dose on production layers with a single compact target. Extending this technology on an advanced optical tool allows for precise measurements of focus and dose errors. This paper will describe the methodology of inline focus and dose monitoring using this technique on 130nm process technology with an outlook on the expectations for future nodes. Results, including focus and dose sensitivity from multiple process steps on production wafers will be shown.
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