KEYWORDS: Transistors, Lithography, Semiconducting wafers, Etching, Photomasks, Optical lithography, Oxides, Silicon, Deep ultraviolet, Process control
We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.
We have investigated the effects of complex barrier structures in double barrier resonant
tunneling diodes (DBRTDs). The largest room temperature peak-to-valley current ratios (PVCR)
to date have been observed for AlGaAs/GaAs DBRTD. PVCRs as high as 5. 1 were observed in
AlAs/GaAs DBRTD with an AL14Ga86As chair barrier in the cathode. We attribute the
improvement in the PVCR to the chair barrier in the cathode which significantly reduces the valley
current. The effects of a real, spatially separated Al,14Ga086As barrier in the anode and cathode
sides of the DBRTDs were also investigated and a PVCR as high as 4.8 was observed when the
A10• 14Ga86As barrier was on the anode side.
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