Boo-Hyun Ham, Il-Hwan Kim, Sung-Sik Park, Sun-Young Yeo, Sang-Jin Kim, Dong-Woon Park, Joon-Soo Park, Chang-Hoon Ryu, Bo-Kyeong Son, Kyung-Bae Hwang, Jae-Min Shin, Jangho Shin, Ki-Yeop Park, Sean Park, Lei Liu, Ming-Chun Tien, Angelique Nachtwein, Marinus Jochemsen, Philip Yan, Vincent Hu, Christopher Jones
As critical dimensions for advanced two dimensional (2D) DUV patterning continue to shrink, the exact process window becomes increasingly difficult to determine. The defect size criteria shrink with the patterning critical dimensions and are well below the resolution of current optical inspection tools. As a result, it is more challenging for traditional bright field inspection tools to accurately discover the hotspots that define the process window. In this study, we use a novel computational inspection method to identify the depth-of-focus limiting features of a 10 nm node mask with 2D metal structures (single exposure) and compare the results to those obtained with a traditional process windows qualification (PWQ) method based on utilizing a focus modulated wafer and bright field inspection (BFI) to detect hotspot defects. The method is extended to litho-etch litho-etch (LELE) on a different test vehicle to show that overlay related bridging hotspots also can be identified.
Aberration sensitivity matching between overlay metrology targets and the device cell pattern has become a common requirement on the latest DRAM process nodes. While the extreme illumination modes used demand that the delta in aberration sensitivity must be optimized, it is effectively limited by the ability to print an optimum target that will meet detectability and accuracy requirements. Therefore, advanced OPC techniques are required to ensure printability and have optimal detectability performance while maintaining sufficient process window to avoid patterning or defectivity issues.
In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.
In order to handle the upcoming 1x DRAM overlay and yield requirements, metrology needs to evolve to more accurately represent product device patterns while being robust to process effects. One way to address this is to optimize the metrology target design. A viable solution needs to address multiple challenges. The target needs to be resistant to process damage. A single target needs to measure overlay between two or more layers. Targets need to meet design rule and depth of focus requirements under extreme illumination conditions. These must be achieved while maintaining good precision and throughput with an ultra-small target. In this publication, a holistic approach is used to address these challenges, using computationally optimized metrology targets with an advanced overlay control loop.
As design rules of advance devices shrink down, not only process-window budget of lithography process is getting tighter, but also CD control to target is more important especially for multiple tool process environment in HVM (High Volume Manufacturing). The tool induced CD bias or CD difference between tools are derived by minute amount of residual imaging parameters even though with strict control in system. The tool to tool CD mismatch is able to be reduced to nanometer or sub-nanometer scale for critical features of concern by using released tools such as LithoTuner PMFCTM (Pattern Matcher Full Chip). During the matching process, tunable imaging parameters such as pupil shape and stage tilt can be used as matching knobs. In this paper, CD mismatch due to film stack change on same exposure tool was studied to check feasibility of PMFC application. Also, CD variation and its impact on CD mismatch by focus error as amount of intrinsic system was investigated as well. By considering the focus impact on CD proximity bias via simple mathematical ways, the CD matching process could be more accurately performed and verified.
We report that, based on our experimental data, lens heating (LH) impact on wafer image can be effectively controlled by using a computational method (cASCAL) on critical device layers with no request on tool time. As design rule shrinks down, LH control plays a key role in preventing the image deterioration caused by the LH-induced wavefront distortion during exposure. To improve LH prediction accuracy, 3-dimension structure of mask stack (M3D) is considered in calculating the electro-magnetic (EM) field that passes through the mask for full chip. Additionally, lens specific calibration (LSC) is performed on individual scanners to take the lens-to-lens variation into account. In data comparisons, we show that cASCAL performs very well as an ASCAL substitute, and that M3D and LSC improve the LH prediction accuracy of cASCAL.
Proximity matching is a common activity in the wafer fabs1,2,3 for purposes such as
process transfer, capacity expansion, improved scanner yield and fab productivity. The
requirements on matching accuracy also become more and more stringent as CD error
budget shrinks with the feature size as technology advances. Various studies have been
carried out, using scanner knobs including NA, inner sigma, outer sigma, stage tilt,
ellipticity, and dose. In this paper, we present matching results for critical features of a
logic device, between an ASML XT:19x0i scanner and an XT:1700i (reference),
demonstrating the advantage of freeform illuminator pupil as part of the adjustable
knobs to provide additional flexibility. We also present the investigation of a novel
method using lens manipulators for proximity matching, effectively injecting scalar
wavefront to an XT:19x0i to mimic the behavior of the XT:1700i lens.
Scanner mismatch has become one of the critical issues in high volume memory production. There are several
components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference
between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more
critical in electrical performance and process window.
In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices.
We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer
metrology data and scanner specific parameters are used to build a computational model, and determine the optimal
settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was
used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil
parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and
measured process window changes by applying the matching sub-recipe are also evaluated.
As K1 factor for mass-production of memory devices has been decreased to almost its theoretical limit, the process
window of lithography is getting much smaller and the production yield has become more sensitive to even small
variations of the process in lithography. So it is necessary to control the process variations more tightly than ever. In
mass-production, it is very hard to extend the production capacity if the tool-to-tool variation of scanners and/or scanner
stability through time is not minimized. One of the most critical sources of variation is the illumination pupil. So it is
critical to qualify the shape of pupils in scanners to control tool-to-tool variations.
Traditionally, the pupil shape has been analyzed by using classical pupil parameters to define pupil shape, but these
basic parameters, sometimes, cannot distinguish the tool-to-tool variations. It has been found that the pupil shape can be
changed by illumination misalignment or damages in optics and theses changes can have a great effect on critical
dimension (CD), pattern profile or OPC accuracy. These imaging effects are not captured by the basic pupil parameters.
The correlation between CD and pupil parameters will become even more difficult with the introduction of more
complex (freeform) illumination pupils.
In this paper, illumination pupils were analyzed using a more sophisticated parametric pupil description (Pupil Fit
Model, PFM). And the impact of pupil shape variations on CD for critical features is investigated. The tool-to-tool
mismatching in gate layer of 4X memory device was demonstrated for an example. Also, we interpreted which
parameter is most sensitive to CD for different applications. It was found that the more sophisticated parametric pupil
description is much better compared to the traditional way of pupil control. However, our examples also show that the
tool-to-tool pupil variation and pupil variation through time of a scanner can not be adequately monitored by pupil
parameters only, The best pupil control strategy is a combination of pupil parameters and simulated CD using measured
illumination pupils or modeled pupils.
Hyper NA system has been introduced to develop sub-60nm node memory devices. Especially memory
industries including DRAM and NAND Flash business have driven much finer technology to improve
productivity. Polarization at hyper NA has been well known as important optical technology to enhance
imaging performance and also achieve very low k1 process. The source polarization on dense structure has
been used as one of the major RET techniques. The process capabilities of various layers under specific
illumination and polarization have been explored.
In this study, polarization characteristic on 40nm memory device will be analyzed. Especially, TE
(Transverse Electric) polarization and linear X-Y polarization on hyper NA ArF system will be compared and
investigated. First, IPS (Intensity in Preferred State) value will be measured with PMM (Polarization
Metrology Module) to confirm polarization characteristic of each machine before simulation. Next simulation
will be done to estimate the CD variation impact of each polarization to different illumination. Third, various
line and space pattern of DRAM and Flash device will be analyzed under different polarized condition to see
the effect of polarization on CD of actual wafer. Finally, conclusion will be made for this experiment and
future work will be discussed.
In this paper, the behavior of 40nm node memory devices with two types of polarization is presented and
the guidelines for polarization control is discussed based on the patterning performances.
The imaging performances of XY linear and TE Azimuthal polarization were compared by thin mask
approximation and rigorous 3D mask simulation. The simulations were performed for 40nm and 44nm half pitch patterns
with a hyper NA (1.35) system. Each polarization state was assumed to have a parametric DOP (degree of polarization)
value that was set to 0.95. Rotated dipole illuminators of several angles were used for the associated tilted patterns to see
the imaging impact by IPS (intensity in the preferred state of polarization) change in the process with XY linear
polarization that has a fixed angle of polarization. The difference in performance between two polarization modes were
compared by NILS and DOF margin. Additionally, the imaging quality of BIM (binary intensity mask) with polarization
beam was studied to that of att-PSM at given process conditions. Two types of available BIM masks of different
thickness were applied to simulation to understand 3D mask simulation impact on the imaging contrast and process
margin. The estimation of two-diffraction beam balance was performed to explain the imaging simulation as well. The
polarization sensitivities of NILS and CD change by DOP were found for each feature with given exposure conditions.
The main purpose of this study is to understand how much overestimation or underestimation of conventional thin mask
simulation could be combined in the process simulation by comparing rigorous 3D mask consideration.
We investigated the influence of lens aberration on the lithographic performance according to the phase error and topography effects of phase-shift mask (PSM). Twin-bar and isolated pattern showing high sensitivity to lens aberration were used for this study. The simulation of aberrated images was carried out using the Solid-CTM simulator. Specially, we quantified the relationship between patterning behaviors such as the isofocal tilt, the left-right (L-R) CD difference and the Z7 and Z9 individual Zernike coefficients. Isofocal tilt aberration sensitivity for Z9 was 0.4nm/nm, which resulted in 2nm CD variation using lens with 5nm Z9 value. When using the lens with 5nm Z7 value, the L-R CD difference and its sensitivity are 10nm and 2nm/nm, respectively. Finally, we evaluated the patterning performance by phase error effect, and determined the phase error criteria for PSM. The pattern placement error was increased by increasing phase error as well as Z7 value, while its slope to the defocus was similar regardless of lens aberration. However, it was found that the aberration sensitivity was not affected by phase error. The simulation predicted that the sensitivity of lens aberration could be increased due to mask topography effect. The nominal shift of phase edge attributed to mask topography was measured.
We demonstrated the impact of space between assist bar and main pattern, width of assist bar, defect size, and the location of defect between assist bar and main pattern on main pattern distortion. The sizes of designed defect on mask were 400, 1600, 3600, and 6400 nm2 (1X) and the locations of defect were varied with 20 nm intervals between assist bar and main pattern. The widths of assist bar were varied from 60nm to 100nm with 10nm intervals and the spacing between assist bar and main pattern with 130- and 150-nm-width were 200nm, 240nm, and 280nm. The ΔCD, which is the difference of CD values between normal main pattern and distorted main pattern adjacent to defects, values were decreased with increasing space between assist bar and main pattern, while width variation of assist bar does not affect on the ΔCD value. Concerning the effect of defect location, we observed that the isolated defects with ≥1600 nm2, located between assist bar and main pattern, were printed on wafer. In sharp contrast, the defect attached to assist bar were not printed at all for all sizes of defects. In addition, ΔCD values were linearly increased as the defect location is close to main pattern regardless of process conditions. These results indicate that the location of defect plays a major role to specify the defect criteria, especially for assist bar OPC mask. The change of process latitude and defect printability with the illumination conditions and mask bias was also investigated
Jun Kyu Ahn, Seon Ho Choi, Young Keun Kim, Ki Yeop Park, Jae Sung Choi, Eun Suk Hong, Kang Sup Shin, Si Bum Kim, Kyeong Keun Choi, Sung Bo Hwang, Jeong Gun Lee
As via first scheme is employed for dual damascene patterning, via filling process has been posed many challenges to the patterning process. For organic BARC assisted dual damascene patterning, differences in etch selectivity between the organic BARC and ILD material generate fence defect problems. It is highly improbable that organic BARC film remains thick enough to protect the via bottom. To reduce the negative impact on the substrate, the BARC material requires to fill small vias. In addition, anti-reflective behavior for KrF lithography, comparable dry-etching and high wet-etching selectivity to the ILD, and compatibility with photoresist processing are necessary for a successful dual damascene patterning. A sacrificial, spin-on 248nm UV absorbing organosiloxane based inorganic BARC has been developed to meet these needs. Inorganic BARC is a material that fills the vias and reduces iso-dense bias for both fill and top coverage and hole-free substrate at trench lithography.
In this paper, the comparison of the performance of inorganic BARC and organic BARC assisted dual damascene patterning with low-k dielectric was conducted. We evaluated the performance of inorganic BARC in terms of the via fill capability, depth of focus, exposure latitude, etch selectivity and etch profile results. The reduction of iso-dense bias from via filling with inorganic BARC instead of organic BARC is discussed.
In this paper, we demonstrated the impact of illumination condition on MEEF and investigated the correlation between CD linearity and MEEF according to the illumination conditions and imaging pitches. For all of the illumination conditions, the MEEF increased appreciably as the CD decreased beyond a CD linear region. The aerial image intensity and NILS change with the pattern size and illumination conditions were also investigated. We also measured and analyzed the printability of mask defect according to the MEEF. Two types of mask defects; chrome and clear mask intrusion defects were designed in the cell. The designed mask defect was split from 0.02 μm2 to 0.72 μm2(5X) in area. While within a linear CD region the slope of the CD response to the defects are similar regardless of the illumination condition and 0.08 μm2(5X) clear defect size was not printed, within a linear CD region the slope of the CD response to the defects increased as the illumination NA decreased and only 0.02 μm2(5X) chrome defect size was printed within a linear CD region, where the defect printability criteria is out side ±5% target CD range. We could also show that as the process is operated under the linearity limit, the dependency of aspect ratio to the defect printability would be increased.
In this paper, we will describe why the calibration process between CD-SEM and transmission electron microscopy (TEM) was performed. TEM is considered to be a unique solution such that we could obtain CD and sidewall angle accurately. TEM has the merit of having good resolution, but the measurement is performed over small segments of device features. The CD measurement error related to line edge roughness (LER) was also investigated in order to avoid the degradation in the accuracy of TEM measurement of CD. Many efforts were performed to reduce the uncertainty in TEM measurement of CD. The amount of the uncertainty related to TEM CD measurement was approximately 5 nm. We could obtain the linear relationship between CD-SEM and TEM measurements of CD Of logic gate lines ranging form 0.12 micrometers to 0.20 micrometers . The average CD measured using TEM was 15 nm lower than the CD measured with CD-SEM at poly silicon etched profile which had the sidewall angle of 86 degrees. Such difference is unacceptable in the CD measurement. The CD measurement error could be compensated with the modification of the measurement algorithms. The reproducibility of CD measurement for various algorithms was also investigated. It was shown that TEM measurement of CD could be applicable for the calibration with CD-SEM measurement to control various processes with different sidewall angles.
The bi-layer resist (BLR) process, which first accomplish imaging on a thin top layer and transfer it down to a thick organic layer, is one of newly emerging patterning techniques in silicon processing. In this work, we studied the lithographic performance of the BLR process adopting FK- SPTM (Fujifilm Olin Co.) as top layer material and various organic material as bottom layer. Generally, considerable advantages of planarization, reduced substrate reflection, improved process latitude, and of enhanced resolution are achieved. However, the resolution and the process latitude are highly affected by surface interaction between the top resist and the bottom material. Moreover, the BLR process has a sidewall roughness problem related to the material factors of the resist and the degraded aerial image contrast, which can affect the reliability of the device. We found that thermal curing treatment applied after development with the consideration of the glass transition temperature are very effective in reducing the line edge roughness. More smooth and steep patterning is achieved by the thermal treatment. The linewidth controllability is below 10 nm and the k1 value is reduced from 0.5 down to 0.32 in this process. The reactive ion etching adopting O2 gas demonstrated selectivity of the top resist over bottom material more than 15:1, together with residue-free and vertical wall profile.
As the integration density of VLSI device increases, the overlay accuracy in the photolithography becomes more and more important. In the sub-quarter micron technology, the registration budget is less than 70 nm. Registration error can be induced by the repeatability error of alignment sensor, mask fabrication error, tool induced shift, process induced shift, and so on. One of these misregistration error sources, overlay parameter difference between DI and FI, can cause significant damage to the device because, in most cases, overlay accuracy is checked only in the mask step. In this paper, we studied the relationship of the Edge Detection Algorithm (EDA) and the overlay mark structure to the wafer scale difference.
Inorganic Anti Reflective Coating (ARC) improves Critical Dimension (CD) uniformity over an exposing field by reducing the reflectivity of the ARC/substrate system in photoresist. A key parameter of the lithographic performance of an inorganic ARC is therefore the reflectivity of the ARC/substrate system in photoresist. But it isn't a directly measurable quantity. In this paper we estimate the reflectivity of the ARC/substrate system in photoresist by measuring the reflectivity swing of the photoresist/ARC/substrate system in air. We also derive a useful relation connecting the reflectivity of the ARC/substrate system in photoresist to that in air. In the case of organic ARC, due to the planarization of the organic ARC on topography, optimization is achieved not by minimizing the reflectivity of the ARC/substrate system in photoresist but by minimizing the variation of the light intensity within the photoresist. The performance of the inorganic and organic ARC for DUV lithography is evaluated, and their differences are investigated.
The print bias between isolated and dense resist pattern (I- D bias) which is originated from the optical proximity effect, is one of the major issues for the processing of randomly arrayed and complicatedly structured logic devices designed with the smaller features than ever. In this study, the characteristics of I-D bias which is related to not only optical parameters but also resist processing parameters were investigated quantitatively through the way of experiment and simulation. Examined processing parameters were as follows: numerical aperture and partial coherence factor ((sigma) ) as the exposure parameters; the ratio of line to space width (duty ratio) as the mask parameter; resist thickness, prebake temperature and post exposure back temperature as the resist processing parameters. The experiments were reviewed in simulation tools such as Prolith2+ and SOLID-C. And the resist patterns were acquired using DUV exposure tool with various kinds of resist.
This paper describes the phase shift mask (PSM) effects in view of production using i-line lithography. For the PSM technology, it was hard to control process because the process condition was limited by the exposure tool. To fabricate the 256MB DRAM with 0.25 micrometers minimum feature size (MFS), we evaluated the PSM including attenuated type for conventional patterns and a 0.25 micrometers cell array using positive and negative tone phase shift mask for actual process. Furthermore, we applied various approaches to get a sufficient depth of focus (DOF) and high resolution using an i-line system with 0.57 NA, an off-axis illumination system, low partial coherence factor, and process in cases of alternating, subresolution, and attenuated type of phase shift mask. As a result, even if pattern delineation was possible, we should optimize design, topology structure, and process to get enough DOF margin, good uniformity, and high repeatability for device fabrication.
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