Ms. Dah-Chung Owe-Yang Profile

Dah-Chung Owe-Yang

Sr. Photolithography Engineer at Shin-Etsu MicroSi Inc

SPIE Involvement:

Author

Proceedings Article | 20 March 2012 Paper

Focus improvement with NIR absorbing underlayer attenuating substructure reflectivity

Wu-Song Huang, Dario Goldfarb, Wai-kin Li, Martin Glodde, Kazumi Noda, Seiichiro Tachibana, Masaki Ohashi, Dah-Chung Owe-Yang, Takeshi Kinsho

Proceedings Volume 8325, 83251A (2012) https://doi.org/10.1117/12.916240

KEYWORDS: Near infrared, Sensors, Semiconducting wafers, Reflectivity, Back end of line, Metals, Optical sensors, Polymers, Coating, Absorption

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Proceedings Article | 4 April 2008 Paper

Development of high-performance tri-layer material

D. Owe-Yang, Toshiharu Yano, Takafumi Ueda, Motoaki Iwabuchi, Tsutomu Ogihara, Shozo Shirai

Proceedings Volume 6923, 69232I (2008) https://doi.org/10.1117/12.774391

KEYWORDS: Silicon, Etching, Reflectivity, Manufacturing, Lithography, Photoresist processing, Coating, Resistance, Antireflective coatings, Immersion lithography

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Proceedings Article | 26 March 2008 Paper

Graded spin-on organic bottom antireflective coating for high NA lithography

Dario Goldfarb, Sean Burns, Libor Vyklicky, Dirk Pfeiffer, Anthony Lisi, Karen Petrillo, John Arnold, Daniel Sanders, Aleksandra Clancy, Robert Lang, Robert Allen, David Medeiros, Dah Chung Owe-Yang, Kazumi Noda, Seiichiro Tachibana, Shozo Shirai

Proceedings Volume 6923, 69230V (2008) https://doi.org/10.1117/12.772268

KEYWORDS: Reflectivity, Polymers, Photoresist materials, Silicon, Etching, Lithography, Optical lithography, Interfaces, Multilayers, Semiconducting wafers

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SPIE Journal Paper | 1 April 2006

Measurements of the dynamic contact angle for conditions relevant to immersion lithography

Scott Schuetter, Timothy Shedd, Keith Doxtator, Gregory Nellis, Chris Van Peski, Andrew Grenville, Shang-Ho Lin, Dah-Chung Owe-Yang

JM3, Vol. 5, Issue 02, 023002, (April 2006) https://doi.org/10.1117/12.10.1117/1.2198540

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Proceedings Article | 4 May 2005 Paper

Double exposure for the contact layer of the 65-nm node

Dah-Chung Owe-Yang, S. S. Yu, Harrison Chen, C. Chang, Bang-Chein Ho, John Lin, Burn Lin

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.599651

KEYWORDS: Image processing, Photomasks, Ultraviolet radiation, Optical lithography, Printing, Photoresist processing, Polymers, Semiconductors, Critical dimension metrology, Image resolution

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The critical dimension (CD) of contact holes for the 65-nm application specific integrated circuit (ASIC) is 100 nm according to the 2002 update of the International Technology Roadmap for Semiconductors. The common through-pitch depth of focus (DOF) of such contact holes is very small using the current ArF exposure tool. High-numerical-aperture (NA) ArF exposure tools are not expected to improve the common DOF that scales by the square of the numerical half aperture. High-transmission attenuated phase-shifting masks increase the DOF of isolated contact holes. Off-axis illumination such as annular or quadrupole illumination improves the DOF of dense contact holes. Nonetheless, both the isolated and the dense contact holes need to be printed within spec on logic circuit. To delineate 100-nm contact holes at several different pitches, we proposed the pack-and-unpack (PAU) process which employs double exposures. First, dummy holes are added to the surroundings of isolated contact holes facilitating the patterning of the resultant dense pattern with a resolution enhancement technique that favors dense contact holes. For example, dense holes are packed to 180-nm pitch and imaged with high-NA lens setting and quadrupole illumination. Then, the second image is used to open the desired holes or block the dummy contact holes. The purpose of this study was to develop new methods and new materials for the patterning of the second image. Three approaches were investigated. The first approach was forming an isolation layer to protect the first image; second, applying UV curing to harden the first image; third, using alcohol-based resists to pattern the second image. Among those three approaches of printing the second image, using resist in alcohols is the most convenient method. Even though the CD control of the second image is not so critical, resolution and process window of resists may need further improvement for 45-nm node and below. Using the second approach allows conventional ArF resists, which does not raise as many concerns as the alcohol-based resists. With the first approach, a lot more work is needed to prevent intermixing and reactions between the isolation layer and the resist for the second image. The results of this work point to the directions for material developments of the PAU process. Both the alcohol-based resists and UV curing are good approaches for PAU. Further characterizations such as DOF, exposure latitude (EL), and mask error factor (MEF) on them will be carried out in the near future.

Proceedings Article | 14 May 2004 Paper

Application of photosensitive BARC and KrF resist on implant layers

D.C. Owe-Yang, Bang-ching Ho, Shinji Miyazaki, Tomohide Katayama, Kenji Susukida, Wenbing Kang, Yung-Cheng Chang

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.534735

KEYWORDS: Critical dimension metrology, Photoresist processing, Lithography, Dry etching, Semiconducting wafers, Antireflective coatings, Bottom antireflective coatings, Reflection, Plasma etching, Chemically amplified resists

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The IC industry is moving toward 90nm node and below. The CD size of implant layers has shrunk to 220nm. To achieve better CD uniformity, dyed KrF resist and top anti-reflective coating (TARC) are commonly used in advanced photo process of implant layers. It’s well known that bottom anti-reflective coating (BARC) has better reflection control over TARC. However, dry etching process is required if typical organic BARC is applied to photo process of implant layers. It is undesirable for two reasons. The first reason is the substrate damage caused by plasma etching could affect the device performance. The second reason is higher cost due to additional processing steps. In order to overcome those two shortcomings, developable BARC (DBARC) is introduced. It is a new type of BARC, which is soluble to developer, TMAH solution, in the resist development step. There are some reports on the developer-soluble KrF BARC. Most of them are polyamic acid and their solubility to alkline could be adjusted by changing bake condition. However, its development is isotropic, which make it difficult to get a vertical profile. Therefore, we have developed a photosensitive developer-soluble BARC (DBARC) which is anisotropic after exposure and thus results in a nice vertical profile. The photosensitive DBARC utilizes the same concept as chemically amplified resist. It has acid-cleavable groups in the resin and PAGs in the formulation. The photosensitive DBARC turns soluble to TMAH developer after exposure and resist PEB. The solubility difference caused by exposure makes developing process anisotropic and thus improves profile control. In this article, we will report the evaluation results of various combinations of KrF resists and DBARC for implant layers. Since both the resist and DBARC are photosensitive, matching of the photo speeds of them is essential. The amount and type of PAG in both the resist and the DBARC play a very import role. Finally, the optimized combination showed acceptable lithography process window and good CD uniformity over topography.

Proceedings Article | 2 June 2003 Paper

Process improvements of applying 193-nm lithography to 90-nm logic implant layer

D.C. OweYang, Harrison Chen, R.M. Deng, Bang-Ching Ho

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483691

KEYWORDS: Lithography, Critical dimension metrology, Scanners, Semiconducting wafers, Logic, Overlay metrology, Arsenic, Optical proximity correction, Scanning electron microscopy, Ion implantation

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Controlling critical dimension (CD) uniformity and overlay accuracy are crucial to achieving quality lithography. The continuous reduction in minimum feature and unit cell sizes on semiconductor wafers has posed significant strain to lithography engineers. According to the 2001 ITRS roadmap, the half pitch of DRAM will be 100 nm and the overlay requirement will be 35 nm for the Poly layer in 2003. Up to date, the 193 nm lithography is mainly applied to those critical layers, such as Poly, Contact, Metal and Via in chip process flow. For the non-criticals, such as well and source-drain implant layers, we still use 248 nm or even 365 nm lithography. Such a situation poses potential challenges when we try to improve the overlay accuracy demanded by area reduction on unit cells since a mix-and-match between 193 nm and 248 nm has to be carried out. In the 90 nm logic process, the overlay requirement of implant layer to critical layers are tightened to 60 nm, which has been close to the current limit of tool matching capability between 193 nm and 248 nm. Stimulated by such an issue we start to implement 193 nm lithography into implant layers. In this paper, a full lithographic process characterization for 90 nm logic implant layers using 193 nm lithography is reported. The photo resist swing cure was first generated to determine the resist thickness. A top antireflective coating (ARC) was also applied to reduce the photo resist swing effect. After the target thickness of photo resist is being defined, three different thickness of resist was coated including targeted, thinner and thicker than targeted. Resist coated wafers were through bombardment of implantation species, then were sent to SIMS analysis. Based on the SIMS results, the target thickness is verified to be safe for the high voltage implantation required by process flow. The DOF data were collected for six kinds of patterns. The proximity effect data of 193 nm is only half of that resulted in 248 nm lithography. So, the optical proximity correction (OPC) may not be needed if 193 nm lithography is used. Besides, the CD variation is also improved when compared to the 248 nm lithography, especially when resist patterns are printed on topographic wafers. As the chip continues its shrinkage, the 193 nm lithography will be a must for implant layers at some point.

Showing 5 of 7 publications

Conference Committee Involvement (9)

Advances in Patterning Materials and Processes XXXI

24 February 2014 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXX

25 February 2013 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXIX

13 February 2012 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXVIII

28 February 2011 | San Jose, California, United States

Advances in Resist Materials and Processing Technology XXVI

23 February 2009 | San Jose, California, United States

Showing 5 of 9 Conference Committees

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