The convergence of microelectronics and photonics on a single chip is one of the greatest challenges of present research. To make it happen, it is necessary to develop an entire novel class of optoelectronic devices exhibiting far beyond the state-of-the-art performance in term of compactness, speed and power efficiency. Silicon photonics enhanced with III-V semiconductors such as InP-based materials is the key technology to provide a platform able with all the necessary functionalities but it is only through the exploitation of nanophotonics concepts that disruptive performance can be reached.
During this presentation, we will show our latest results obtained on electrically powered InP-on-SOI photonic crystal devices. These results will concern first the demonstration of nanolaser diodes emitting at 1.55µm in a SOI waveguide with a wall-plug efficiency higher than 10%. The developed electrical injection scheme allows us, also, to conceive nano-amplifiers and electro-optical modulators which show promising features for their integration in a photonic circuit.
As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption.
Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on–chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
We present the first characterization results of some cascaded interleavers that we have recently fabricated on 4 μm thick Silicon on Insulator (SOI) wafers. The filters are based on strip waveguides, micron-scale bends and compact MMIs, all components with low loss and high tolerance to fabrication errors, due to the high mode confinement in the silicon region. A thorough comparison of the found results with the theoretical model will be presented, taking into account fabrication limitations. The fabricated filters will be used in the optical RAM circuits of the RAMPLAS project funded by the European Commission.
Hybrid integration on Silicon-on-Insulator (SOI) has emerged as a practical solution for compact and high-performance
Photonic Integrated Circuits (PICs). It aims at combining the cost-effectiveness and CMOS-compatibility benefits of the
low-loss SOI waveguide platform with the versatile active optical functions that can be realized by III-V photonic
materials. The utilization of SOI, as an integration board, with μm-scale dimensions allows for an excellent optical mode
matching between silicon rib waveguides and active chips, allowing for minimal-loss coupling of the pre-fabricated IIIV
components. While dual-facet coupling as well as III-V multi-element array bonding should be employed to enable
enhanced active on-chip functions, so far only single side SOA bonding has been reported. In the present
communication, we present a novel integration scheme that flip-chip bonds a 6-SOA array on 4-μm thick SOI
technology by coupling both lateral SOA facets to the waveguides, and report on the experimental results of wavelength
conversion operation of a dual-element Semiconductor Optical Amplifier – Mach Zehnder Interferometer (SOA-MZI)
circuit. Thermocompression bonding was applied to integrate the pre-fabricated SOAs on SOI, with vertical and
horizontal alignment performed successfully at both SOA facets. The demonstrated device has a footprint of 8.2mm x
0.3mm and experimental evaluation revealed a 12Gb/s wavelength conversion operation capability with only 0.8dB
power penalty for the first SOA-MZI-on-SOI circuit and a 10Gb/s wavelength conversion operation capability with 2 dB
power penalty for the second SOA-MZI circuit. Our experiments show how dual facet integration can significantly
increase the level of optical functionalities achievable by flip-chip hybrid technology and pave the way for more
advanced and more densely PICs.
Semiconductor optical amplifiers (SOAs) are a well-established solution of optical access networks. They could prove an
enabling technology for DataCom by offering extended range of active optical functionalities. However, in such costand
energy-critical applications, high-integration densities increase the operational temperatures and require powerhungry
external cooling. Taking a step further towards improving the cost and energy effectiveness of active optical
components, we report on the development of a GaInNAs/GaAs (dilute nitride) SOA operating at 1.3μm that exhibits a
gain value of 28 dB and combined with excellent temperature stability owing to the large conduction band offset
between GaInNAs quantum well and GaAs barrier. Moreover, the characterization results reveal almost no gain
variation around the 1320 nm region for a temperature range from 20° to 50° C. The gain recovery time attained values as short as 100 ps, allowing implementation of various signal processing functionalities at 10 Gb/s. The combined
parameters are very attractive for application in photonic integrated circuits requiring uncooled operation and thus
minimizing power consumption. Moreover, as a result of the insensitivity to heating issues, a higher number of active
elements can be integrated on chip-scale circuitry, allowing for higher integration densities and more complex optical
on-chip functions. Such component could prove essential for next generation DataCom networks.
We present novel deeply etched functional components, fabricated by multi-step patterning in the frame of our 4 μm
thick Silicon on Insulator (SOI) platform based on singlemode rib-waveguides and on the previously developed rib-tostrip
converter. These novel components include Multi-Mode Interference (MMI) splitters with any desired splitting
ratio, wavelength sensitive 50/50 splitters with pre-filtering capability, multi-stage Mach-Zehnder Interferometer (MZI)
filters for suppression of Amplified Spontaneous Emission (ASE), and MMI resonator filters. These novel building
blocks enable functionalities otherwise not achievable on our SOI platform, and make it possible to integrate optical
RAM cell layouts, by resorting to our technology for hybrid integration of Semiconductor Optical Amplifiers (SOAs).
Typical SOA-based RAM cell layouts require generic splitting ratios, which are not readily achievable by a single MMI
splitter. We present here a novel solution to this problem, which is very compact and versatile and suits perfectly our
technology. Another useful functional element when using SOAs is the pass-band filter to suppress ASE. We pursued
two complimentary approaches: a suitable interleaved cascaded MZI filter, based on a novel suitably designed MMI
coupler with pre-filtering capabilities, and a completely novel MMI resonator concept, to achieve larger free spectral
ranges and narrower pass-band response. Simulation and design principles are presented and compared to preliminary
experimental functional results, together with scaling rules and predictions of achievable RAM cell densities. When
combined with our newly developed ultra-small light-turning concept, these new components are expected to pave the
way for high integration density of RAM cells.
Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.