Classical SEM metrology, CD-SEM, uses low data rate and extensive frame-averaging technique to achieve high-quality SEM imaging for high-precision metrology. The drawbacks include prolonged data collection time and larger photoresist shrinkage due to excess electron dosage. This paper will introduce a novel e-beam metrology system based on a high data rate, large probe current, and ultra-low noise electron optics design. At the same level of metrology precision, this high speed e-beam metrology system could significantly shorten data collection time and reduce electron dosage. In this work, the data collection speed is higher than 7,000 images per hr. Moreover, a novel large field of view (LFOV) capability at high resolution was enabled by an advanced electron deflection system design. The area coverage by LFOV is >100x larger than classical SEM. Superior metrology precision throughout the whole image has been achieved, and high quality metrology data could be extracted from full field. This new capability on metrology will further improve metrology data collection speed to support the need for large volume of metrology data from OPC model calibration of next generation technology. The shrinking EPE (Edge Placement Error) budget places more stringent requirement on OPC model accuracy, which is increasingly limited by metrology errors. In the current practice of metrology data collection and data processing to model calibration flow, CD-SEM throughput becomes a bottleneck that limits the amount of metrology measurements available for OPC model calibration, impacting pattern coverage and model accuracy especially for 2D pattern prediction. To address the trade-off in metrology sampling and model accuracy constrained by the cycle time requirement, this paper employs the high speed e-beam metrology system and a new computational software solution to take full advantage of the large volume data and significantly reduce both systematic and random metrology errors. The new computational software enables users to generate large quantity of highly accurate EP (Edge Placement) gauges and significantly improve design pattern coverage with up to 5X gain in model prediction accuracy on complex 2D patterns. Overall, this work showed >2x improvement in OPC model accuracy at a faster model turn-around time.
Sub-Resolution Assist Feature (SRAF) printing detection is critical during SRAF model building. Currently, SRAF printing detection on silicon wafer is mainly through human judgement on CDSEM images, which is inefficient and error prone. Therefore, a robust automatic SRAF printing classification mechanism is essential to improve detection accuracy and efficiency. This paper presents a method of classifying SRAF printing based on a database-independent contour extraction algorithm. By size calculation on extracted contour SRAF feature printing classification can be made automatically. This flow has been demonstrated to be able to correctly classify SRAF printing with consistent performance thus avoid the subjectivity and inconsistency in human judgement.
In optical proximity correction (OPC), the sub-resolution assist feature (SRAF) has been used to enhance the process window of main structures. However, the printing of SRAF on wafer is undesirable as this may adversely degrade the overall process yield if it is transferred into the final pattern. A reasonably accurate prediction model is needed during OPC to ensure that the SRAF placement and size have no risk of SRAF printing. Current common practice in OPC is either using the main OPC model or model threshold adjustment (MTA) solution to predict the SRAF printing. This paper studies the feasibility of SRAF printing prediction using logistic regression (LR). Logistic regression is a probabilistic classification model that gives discrete binary outputs after receiving sufficient input variables from SRAF printing conditions. In the application of SRAF printing prediction, the binary outputs can be treated as 1 for SRAFPrinting and 0 for No-SRAF-Printing. The experimental work was performed using a 20nm line/space process layer. The results demonstrate that the accuracy of SRAF printing prediction using LR approach outperforms MTA solution. Overall error rate of as low as calibration 2% and verification 5% was achieved by LR approach compared to calibration 6% and verification 15% for MTA solution. In addition, the performance of LR approach was found to be relatively independent and consistent across different resist image planes compared to MTA solution.
With the introduction of negative tone develop (NTD) resists to production lithography nodes, multiple NTD resist modeling challenges have surpassed the accuracy limits of the existing modeling infrastructure developed for the positive polarity process. We report the evaluation of two NTD resist modeling algorithms. The new modeling terms represent, from the first principles, the NTD resist mechanisms of horizontal shrink and horizontal development bias. Horizontal shrink describes the impact of the physical process of out-gassing on remaining resist edge location. Horizontal development bias accounts for the differential in the peak and minimum development rate with exposure intensity observed in NTD formulations. We review specific patterning characteristics by feature type, modeling accuracy impact presented by these NTD mechanisms, and their description in our compact models (Compact Model 1, CM1). All the new terms complement the accuracy advantage observed with existing CM1 resist modeling infrastructure. The new terms were tested on various NTD layers. The results demonstrate consistent model accuracy improvement for both calibration and verification. Furthermore, typical NTD model fitting challenges, such as large SRAF-induced wafer CD jump, can be overcome by the new NTD terms. Finally, we propose a joint-tuning approach for the calibration of compact models for the NTD resist.
A robust optical proximity correction (OPC) model must include process variation to be effective in volume manufacturing. Often, calibration of an OPC model is based on data from a single scanner. However, scanner and mask three dimension (3D) effects have been found to affect printing performance and OPC model effectiveness [1]. OPC model robustness is improved if the fingerprints of different scanners are matched as closely as possible. Scanner source map or boundary condition variations can cause isolated and dense feature focus differences between different scanners. The scanner used to build a robust OPC model should have a minimum focus difference between isolated and dense features. Mask 3D effects must be included in OPC model building. Even if the design data is the same, mask 3D effects will vary by different advanced blank film stacks and model fitting will lead to different results. In this work, the effects of focus differences between nested and isolated features for OPC model building are quantified. In addition, mask 3D effect contributions to OPC models will also be illustrated. OPC model tolerance to variation is shown using data from multiple scanners and mask topographies and methodologies to optimize OPC models are presented. The data confirms that different absorber thickness, and n and k values, for advanced binary masks will influence the boundary conditions and effect lithographic performance. A thinner absorber demonstrated better CD prediction than thicker blanks in semi-dense and isolated patterns for both CDTP and inverse CDTP. It also shows that the thinner absorber has better inverse linearity in small isolated features, and has much better prediction for large isolated patterns. The generation of OPC models must include variations due to mask material properties and scanner optical variations to provide robust performance in manufacturing.
For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.
Source Mask Optimization (SMO) has become an integral part of resolution enhancement techniques (RET) for almost all critical layers at advanced technology nodes. Over the past couple of years, various flows have emerged for integrating SMO into mainstream RET selection. These flows revolve mainly around clip selection, resist model, verification and analysis metrics, design rule optimization, and so on. There has also been strong emphasis on the quality of mask that is conjugated for source selection process. All these variations in analysis and rigorous simulations for flow selection are critical but they also create a bottleneck in overall RET development. In this paper, we demonstrate an initial RET development flow for 20 nm technology with emphasis on quantifying benefits coming from source and mask. We also report challenges that are encountered in the foundry environment when moving from RET development to production. In conclusion, we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for a production environment.
Due to the continuous shrinking in half pitch and critical dimension (CD) in wafer processing, maintaining a reasonable
process window such as depth of focus (DOF) & exposure latitude (EL) becomes very challenging. With the source
mask optimization (SMO) methodology, the lithography process window can be improved and a smaller mask error
enhancement factor (MEEF) can be achieved.
In this paper, the Tachyon SMO work flow and methodology was evaluated. The optimum source was achieved through
evaluation of the critical designs with Tachyon SMO software and the simulated performance was then verified on
another test case. Criteria such as DOF, EL & MEEF were used to determine the optimum source achieved from the
evaluation. Furthermore, the process variation band (PV-Band) and the number of hot spot (design weak points) were
compared between the POR and the optimum source. The simulation result shows the DOF, MEEF & worst PV-Band
were improved by 13%, 17% & 12%, respectively with the optimum SMO source.
In order to verify the improvement from the optimum SMO at the silicon level, a new OPC model was recalibrated with
wafer CD from the optimized source. The OPC recipe was also optimized and a reticle was retrofitted with the new OPC.
By comparing the process window, hotspots and defects between the original vs. new reticle, the benefit of the optimized
source was verified on silicon.
KEYWORDS: 3D modeling, Data modeling, Photomasks, Calibration, Performance modeling, Semiconducting wafers, Optical proximity correction, Systems modeling, Panoramic photography, System on a chip
As mask feature sizes have shrunk well below the exposure wavelength, the thin mask of Kirchhoff approximation
breaks down and 3D mask effects contribute significantly to the through-focus CD behavior of specific features.
While full-chip rigorous 3D mask modeling is not computationally feasible, approximate simulation methods do
enable the 3D mask effects to be represented. The use of such approximations improves model prediction capability.
This paper will look at a 28nm darkfield and brightfield layer datasets that were calibrated with a Kirchhoff model
and with two different 3D-EMF models. Both model calibration accuracy and verification fitness improvements are
realized with the use of 3D models.
With shrinking feature sizes and error budgets in OPC models, effective pattern coverage and accurate measurement
become more and more challenging. The goal of pattern selection is to maximize the efficiency of gauges used in model
calibration. By optimizing sample plan for model calibration, we can reduce the metrology requirement and modeling
turn-around time, without sacrificing the model accuracy and stability. With the Tachyon pattern-selection-tool, we seek
to parameterize the patterns, by assessing dominant characteristics of the surroundings of the point of interest. This
allows us to represent each pattern with one vector in a finite-dimensional space, and the entire patterns pool with a set
of vectors. A reduced but representative set of patterns can then be automatically selected from the original full set
sample data, based on certain coverage criteria. In this paper, we prove that the model built with 56% reduced wafer data
could achieve comparable quality as the model built with full set data.
KEYWORDS: Critical dimension metrology, Optical proximity correction, Silicon, Lithography, Data modeling, Reticles, Semiconducting wafers, Control systems, Light scattering, Process control
Optical proximity correction (OPC) plays a vital role in the lithography process for critical dimension (CD) control.
With the shrinking of the design rule, CD is more sensitive to lithography process, so the task for OPC becomes more
challenging. Flare, or stray light, is an added incoherent background intensity that will detract from lithography system
performance, CD control and process latitude. The impact of flare on lithographic imaging and its correction through
OPC has been the subject of increased investigation.
In this paper, the flare effects on CD variation by changing the total image intensity are discussed. The flare map is
obtained by running the flare model on the mask layout. Based on the flare map, flare test patterns are designed and flare
test reticle is written. After collecting wafer silicon data with CD SEM, flare model is verified and the flare impacts on
the across chip line width variation (ACLV) are presented. With the existence of flare, CD bias across different areas of
the cell could be measured. As CD varies by a comparatively wider range than optical proximity range, it could not be
corrected by existing OPC model. Based on the analysis of flare model and the experiment results, applications on flare
correction are discussed by using OPC.
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