Ms. Ewa Kasperkiewicz Profile

Ewa Kasperkiewicz

at ASML Netherlands BV

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Publications (2)

Proceedings Article | 1 December 2022 Presentation + Paper

Direct correlation between mask registration and on-wafer measurements for individual logic device features

Richard van Haren, Steffen Steinert, Orion Mouraille, Ewa Kasperkiewicz, Jan Hermans, Mahmudul Hasan, Leon van Dijk, Dirk Beyer

Proceedings Volume 12293, 122930L (2022) https://doi.org/10.1117/12.2641618

KEYWORDS: Photomasks, Semiconducting wafers, Logic, Image registration, Overlay metrology, Scanners, Metrology, Scanning electron microscopy, Optical alignment, Logic devices

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In all investigations that we performed over the past years; it has been clearly demonstrated that the off-line mask-to-mask overlay as determined on the Zeiss PROVE tool correlates very well with the on-wafer measurements. It all started off with a correlation study utilizing wafer alignment marks. Wafer alignment marks are metrology structures that can be read out inside ASML scanners by the wafer alignment sensor. In that work, the impact of the reticle alignment marks required to align the mask inside the scanner was incorporated as well. An excellent correlation (R2 < 0.96) was shown with an accuracy of 0.58-nm. This result was achieved after carefully setting up an experiment in photoresist and by ruling out any other additional overlay contributors other than mask and the scanner baseline overlay performance. After this initial success, we continued the investigation by considering µ-DBO (Diffraction Based Overlay) metrology targets that can be read out on an ASML Yieldstar (YS:375) overlay metrology tool. In this work, the complexity of the experiment was increased. Instead of using only photo resist, an industry relevant process Litho-Etch process flow was selected. The mask was written on a state-of-the-art writing tool (EBM-9000). Again, excellent correlation coefficients (R2 < 0.92) were obtained. This time within the sub-nanometer range at wafer level. During the execution of that work, an error source that contributes to the small mismatch (< 0.14-nm) between mask and on-wafer measurements was addressed: the sampling scheme difference of the signal generating areas. While the PROVE tool has been designed to measure local (feature) placement errors, this is not the case for an overlay metrology tool or the scanner wafer alignment sensor. For the latter two metrology systems, a position is obtained from a much larger region of interest (ROI) for which local placement errors are averaged out. The observed mismatch can easily be mitigated by increasing the number of PROVE measurements with a small ROI to match it with the ROI of the overlay metrology tool or the wafer alignment sensor. While studying the increasing number of local registration measurements by the PROVE tool, an interesting observation was made. The way the mask had been written on the mask e-beam writer seemed to be reflected in the residual local registration measurements! Stripes were observed that appear to be running across the full width of the mask. Since the typical dimensions of the stripes at wafer level are small compared to the areas that are used for overlay measurements and/or wafer alignment measurements, they are hard to detect on wafer by using optical techniques. In this follow-up work, we explore the correlation between mask registration measurements and the on-wafer measurement for individual device features. This means that we make another step-in complexity, the length scales of interest are now significantly below the typical dimensions of an overlay metrology target. To continue the correlation study, a large field of view SEM is required to measure the relative positions of the device features. We show that the way the mask has been written can indeed be found back on wafer! Although the local placement errors for a single logic device feature is in the order of ~0.5-nm at wafer level, we show that the correlation between mask measurements and wafer measurement still holds. This enables an interesting new application space that is addressed in the current paper.

Proceedings Article | 22 February 2021 Presentation + Paper

Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Kuan-Ming Chen, Wolfgang Henke, Ji-Hoon Jung, Ewa Kasperkiewicz, Anita Bouma, Rizvi Rahman, Gratiela Isai, Gwang-Gon Kim, Sotirios Tsiachris, Jae-Doug Yoo, Yuna Park, JaeYoung Park, Jonggeun Won, Nang-Lyeom Oh, Hsin-Yu Chen, WeiTai Lin, Chih-Hung Hsieh, Kuo-Feng Pao, Kyoyeon Cho, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Taekwon Jee, Seung-Uk Jeong, Jeongwoo Jae, Sang-Woo Kim, Dongyoung Lee, Jungchan Kim, WonKwang Ma, Sang-Ho Lee, Chan-Ha Park

Proceedings Volume 11611, 116111V (2021) https://doi.org/10.1117/12.2584149

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Overlay metrology, Optical lithography, Metrology, Visualization, Statistical analysis, Lithography, Graphic design, Etching

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