The 0.35μm HV-CMOS process technology utilizes several junctions with different doping levels and depths. This process supports complete modular 3V and 5V standard CMOS functionality and offers a wide set of HV transistor types capable for operating voltages from 20V to 120V made available with only 2 more mask adders [1]. Compared to other reported integration of photo detection functionalities in normal CMOS processes [2] or special modified process technologies [3] a much wider variety of junction combinations is already intrinsically available in the investigated technology. Such junctions include beside the standard n+ and p+ source/drain dopings also several combinations of shallow and deep tubs for both p-wells and n-wells. The availability of junction from submicron to 7μm depths enables the selection of appropriate spectral sensitivity ranging from ultraviolet to infrared wavelengths. On the other side by appropriate layouts the contributions of photocurrents of shallower or deeper photo carrier generation can be kept to a minimum. We also show that by analytically modelling the space charge regions of the selected junctions the drift and diffusion carrier contributions can be calculated with a very good match indicating also the suppression of diffusion current contribution. We present examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 380-450nm, 450-600nm or 700-900nm. By appropriate junction choice the ratios of the generated photo currents in their respective peak zones can exhibit more than a factor of 10 compared to the other photo diode combinations. This enables already without further filter implementation a very good spectral resolution for colour sensing applications. Finally the possible junction combinations are also assessed by the achievable dark current for optimized signal to noise characteristic.
We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting
with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping
concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality
of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping
concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the
CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as
host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD
protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer
fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors
could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain
those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS
processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low
doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special
implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates
we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse
voltage.
PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors,
charge-coupled devices and pulse oximeters for medical applications. The possibility to combine and to integrate the
fabrication of the sensor with its signal conditioning circuitry in a CMOS process allows device miniaturization in
addition to enhance its properties lowering the production and assembly costs. This paper presents the design and
characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low
impurity substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices
with a minimum dark current. The dark current is studied, analyzed and measured for two different starting materials and
for different geometries. A model previously proposed is reviewed and compared with experimental data.
Silicon photonics have generated an increasing interest in the recent year, mainly for optical
telecommunications or for optical interconnects in microelectronic circuits. The rationale of silicon photonics
is the reduction of the cost of photonic systems through the integration of photonic components and an IC on a common chip, or in the longer term, the enhancement of IC performance with the introduction of optics inside
a high performance chip.
In order to build a Opto-Electronic Integrated circuit (OEIC), a large European project HELIOS has been
launched two years ago. The objective is to combine a photonic layer with a CMOS circuit by different
innovative means, using microelectronics fabrication processes. High performance generic building blocks
that can be used for a broad range of applications are developed such as WDM sources by III-V/Si
heterogeneous integration, fast Si modulators and Ge or InGaAs detectors, Si passive circuits and specific
packaging. Different scenari for integrating photonic with an electronic chip and the recent advances on the
building blocks of the Helios project are presented.
We report on monolithically integrated PIN photodiodes whose responsivity values could be significantly enhanced over
the whole spectral range by the implementation of a Bottom Antireflective Coating (BARC) process module into
austriamicrosystems 0.35μm CMOS as well as high-speed SiGe BiCMOS technologies. The resulting photodiodes
achieve excellent responsivities together with low capacitances and high bandwidths. We processed finger-photodiodes
with interdigitated n+ cathodes, which are especially sensitive at low wavelengths, and photodiodes with full area n+
cathodes on very lightly p-doped start material. We present a method of depositing an antireflective layer directly upon
the Si surface of the photodiode by changing the standard process flow as little as possible. With just one additional mask
alignment and a well controlled etch procedure we manage to remove the thick intermetal oxide and passivation nitride
stack over the photodiodes completely without damaging the Si surface. The following deposition of a CVD Silicon
Nitride BARC layer not only minimizes the reflected fraction of the optical power but also acts as passivation layer for
the photodiodes. Another benefit of BARC processing is the fact that in-wafer and wafer-to-wafer quantum efficiency
variations can be dramatically reduced. In our experiments we deposited BARC layers of different thicknesses that were
optimised for violet, red and infrared light. Responsivity measurements resulted in values as high as R=0.27A/W at
λ=410nm, R=0.53A/W at λ=670nm and R=0.5A/W at λ=840nm.
PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors,
charge-coupled devices, and pulse oximeters. The possibility to combine and to integrate the fabrication of the sensor
with its signal conditioning circuitry in a CMOS process flow opens the window to device miniaturization enhancing its
properties and lowering the production and assembly costs. This paper presents the design and characterization of silicon
based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity float zone substrate
is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark
current. The photodiodes in the array are isolated by a guard ring consisting of a n+-p+ diffusions. However, the
introduction of the guard ring design, necessary for photodiode-to-photodiode isolation, leads to an increase of the
photodiodes dark current. In this article, the new parasitic term on the dark current is identified, formulated, modelled
and experimental proven and has finally been used for an accurate design of the guard ring.
We present an improvement of monolithically integrated photodiodes in a p-type substrate of a commercial high-speed 0.35μm SiGe heterojunction bipolar transistor (HBT) BiCMOS technology. These photodetectors (PDs) combine low capacitance with high bandwidth and responsivity. Slight process modifications of the standard HBT process have been introduced in order to decrease leakage currents and enhance reach-through stability of the PDs. These modifications
have been chosen carefully in order not to alter any other transistor parameters as shown in [1]. To enable low capacitances of the PDs very lightly p-doped epitaxially grown layers of different thicknesses over highly p-doped substrates have been investigated. The improvement becomes manifest, e.g. in a bandwidth of 557MHz and a responsivity of 0.19A/W of a finger photodiode at blue light and a reverse bias voltage of 4V in a 10μm cathode digit-spacing configuration. The capacitance of this finger photodiode is 150fF, overtopping the regular PIN photodiode published in [2] for
the same light-sensitive area with a capacitance of 225fF. Results of detectors with interdigitated cathode distances of 5μm, 10μm, 15μm and 30μm are presented over the wide spectrum of technologically significant optical wavelengths from near-infrared to blue and ultraviolet. These detectors fulfil the requirements demanded by photodiode integrated circuits for universal backward compatible optical storage systems.
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