Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to cost, yield, and manufacturability. In this paper, we present a simulated annealing based floorplanner to solve the shuttle mask floorplanning problem with multiple optimization objectives and constraints. We will consider area minimization, density optimization (for manufacturability enhancement with CMP), wafer utilization maximization, die-to-die inspection constraint, die orientation constraint and their combinations. A nice property of our floorplanner is that it can be easily adapted to different cost models of mask and wafer manufacturing. Experiments on industry data show promising results.
A shuttle mask has different chips on the same mask. The chips are not electrically connected. Alliance and foundry customers can utilize shuttle masks to share the rising cost of mask and wafer manufacturing. This paper studies the shuttle mask floorplan problem, which is formulated as a rectangle-packing problem with constraints of final die sawing strategy and die-to-die mask inspection. For our formulation, we offer a "merging" method that reduces the problem to an unconstrained slicing floorplan problem. Excellent results are obtained from the experiment with real industry data. We also study a "general" method and discuss the reason why it does not work very well.
KEYWORDS: Sensors, Detection and tracking algorithms, Telecommunications, Signal detection, Signal to noise ratio, Computing systems, Binary data, Gold, Clocks, Modulation
The multistage detection algorithm has been widely accepted as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time implementation of this detection algorithm in the uplink system, where we have achieved both high performance in the interference cancellation and computational efficiency. When interference cancelation converges, the difference of the detection vectors between two consecutive stages is mostly zero. We recode the estimation bits, mapping from plus or minus 1 to 0 and plus or minus 2. Bypassing all the zero terms saves computations. Multiplication by plus or minus 2 can be easily implemented in hardware as arithmetic shifts. The system delay of a three-stage detector can be reduced by half with satisfactory bit error rate. We also propose a VLSI implementation of this algorithm that has the potential of real-time performance. The detector handling up to eight users with 12-bit fixed point precision was fabricated using a 1.2 micrometer CMOS technology.
Four different molecule-design films with azobenzene chromophore were investigated in our experiment, which were the guest-host system, the side-chain system, the crosslinked system and the diazo side-chain system. The decaying processes of them were presented and compared in pair. The differences between them were explained with respect to their different molecule design.
Employing all-optical poling technique, we propose a novel method of optical storage based on the mechanism of photoinduced isomerization and reorientation of azobenzenes. The recording of an optical binary image was experimentally demonstrated in an azo-dye doped polymer film. The recorded information can be permanently stored and also can be erased rapidly with a circularly polarized light. Furthermore, a wavelength conversion of optical image can be obtained using such method.
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