Spin-on-carbon hard mask (SOC HM) has been used in semiconductor manufacturing since 45nm node as an alternative carbon hard mask process to chemical vapor deposition (CVD). As advancement of semiconductor to 2X nm nodes and beyond, multiple patterning technology is used and planarization of topography become more important and challenging ever before. In order to develop next generation SOC, one of focuses is planarization of topography. SOC with different concepts for improved planarization and the influence of thermal flow temperature, crosslink, film shrinkage, baking conditions on planarization and filling performance are described in this paper.
Photoresists play a key role in enabling the patterning process, and the development of their chemistry has contributed significantly to the industry’s ability to continue shrinking device dimensions. However, with the increasing complexity of patterning ever smaller features, photoresist performance needs to be supported by a large number of materials, such as antireflective coatings and anti-collapse rinses. Bottom anti-reflective coatings are widely used to control reflectivity-driven pattern fidelity in i-line and DUV exposures. While no such reflectivity control is required at EUV wavelengths, it has been demonstrated that use of an EUV underlayer (EBL) coating with high EUV photon absorption (EPA) unit can improve resist performance such as sensitivity and resist-substrate poisoning, thereby improving resolution and process window. EBL can also help to reduce the effect of out-of-band (OoB) irradiation. Traditionally, final photoresist image cleaning after the develop step has been performed using de-ionized water, generally known as a “rinse step”. More recently pattern collapse has developed to a major failure mode in high resolution lithography attributed to strong capillary forces induced by water resulting in pattern bending (‘pattern sticking’) or adhesion failure. With decreasing feature geometries (DPT immersion lithography, EUV) the benefit of rinse solutions to prevent pattern collapse has increased. In addition such rinse solutions can in some cases improve defects and LWR. In this paper we describe the advantages of AZ® EBL series of EUV underlayer materials and EUV FIRM® EXTREME™ rinse solutions when applied individually and in combinations. It is demonstrated that the use of underlayer materials can help improve LWR through improvement of resist profiles. Use of FIRM® EXTREME™ rinse is shown to provide significant improvement in collapse margin and total defect counts.
The negative tone development (NTD) process has proven benefits for superior imaging performance in 193nm
lithography. Shrink materials, such as AZ® RELACS® have found widespread use as a resolution enhancement
technology in conventional 248nm (DUV), 193 nm dry (ArF) and 193 nm immersion (ArFi) lithography. Surfactant
rinses, such as AZ® FIRM® are employed as yield enhancement materials to improve the lithographic performance by
avoiding pattern collapse, eliminating defects, and improving CDU. This paper describes the development and recent
achievements obtained with new shrink and rinse materials for application in NTD patterning processes.
Dual damascene technique has been widely applied to IC device fabrication in copper interconnect
process. For traditional via-first dual damascene application, a fill material is first employed to fill via to protect
over-etching and punch-through of the bottom barrier layer during the trench-etch process. Etch-back process is then
applied to remove excess overfill thickness and maintain a greater planar topography. To get better CD control, a thin
organic BARC is finally coated to reduce reflectivity for trench patterning but not in this study. It is a multi-step and
costly dual damascene process. In this study, a new gap-filling BARC material with good via fill and light
absorption features was adopted to explore the via-first dual damascene process by skipping etch-back and BARC
coating steps. The results show not only the reduction of process cycle time and cost saving but also the CP yield
improvement based on data from pilot production of 0.11/0.13 μm logic device.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.