In this paper, we present a rigorous simulation engine for DSA chemo-epitaxy patterning processes. The model can be utilized to predict the post-process patterns for line space and hexagonal hole layouts. Traditional pitch-split and EUV pattern rectification process integration schemes are simulated. The model output for Line Edge Roughness (LER) and Pattern Placement Error (PPE) is compared to the experimental results. Finally, we will explore how to enable DSA-aware process-compliant designs, taking into account cut-mask considerations in the context of design rules.
BackgroundFor complex two-dimensional (2D) patterns, optical proximity correction (OPC) model calibration flows cannot always satisfy accuracy requirements with the standard cutline-based input data. Utilizing after-development inspection e-beam metrology image contours, better model predictions of 2D shapes and wafer hotspots can be realized.AimWe compare model accuracy performance of conventional cutline-based and contour-based OPC models on the regular and hotspots patterns.ApproachBy utilizing image contours that are directly extracted from large field of view (LFoV) e-beam metrology, OPC models were calibrated and verified with both cutline-based and contour-based modeling flows. We also used a wafer sampling plan that contained bridging hotspots. Using that sampling plan, a hotspot-aware three-dimentional resist (R3D) compact model was created.ResultsFirst, a contour-based OPC model was generated with <1 nm root mean square error of contour sites. Compared with cutline-based models, it shows better predictions on 2D feature corners. Second, when combined with a hotspot sampling plan, a hotspot-aware compact model could be generated. The accuracy of hotspot predictions on false positives and false negatives was reduced to around 1% with this approach.ConclusionsOPC model calibration and verification with LFoV image contours provide improved predictions on corner rounding shapes and great potential to increase design space coverage. We also observed improved accuracy of hotspot predictions when using an update hotspot aware model when comparing with that of the OPC model. Furthermore, the combination of R3D and stochastic compact models also demonstrated great potential on predictions of rare wafer failure events.
Typical photoresists processes include a small set of photo-chemical reactions, with each reaction represented by many statistically identically distributed and independent instances. These instances eventually combine into the resist deprotection function, resulting, by virtue of the Central Limit Theorem, in Gaussian Random Field deprotection models. We discuss and demonstrate the approaches to calibration of such models, based on experimentally measured edges of lithographic features, their LER, LWR and PSD. We also present, discuss and analyze the phenomenon of “spatial ergodicity” and its effect on proper sampling of edge measurements for stochastic model calibration.
The fast rigorous model (FRM) is a first principles solver based on sequential simulations of photochemical reactions in photoresists. We report the evaluation of FRM relative to compact models (CM1) for NTD OPC model accuracy. We demonstrate equivalent or better accuracy to CM1 when FRM is combined with a CM1 model of the same composition. In the case of CTR to FRM comparison, FRM is 34% more accurate in calibration and prediction on average across 20 testcases. FRM is 5% more predictive than the most complex CM1 modelform tested with similar calibration accuracy. FRM supplemented with limited CM1 terms provides better verification accuracy for SRAF printing and hotspot detection. Further, the input data needed to train the FRM model in order to achieve high predictive accuracy is a fraction (1-5%) of that needed by more complex CM1 modelforms. Finally, we show through the Akaike Information Criteria method that FRM is more predictive than an equivalent CM1 model based on the degrees of freedom in the modelform and quantity of data available.
KEYWORDS: Optical proximity correction, Electron beam lithography, 3D modeling, Inspection, Calibration, Lithography, Data modeling, Time metrology, Semiconducting wafers, Scanning electron microscopy
A method to perform Optical Proximity Correction (OPC) model calibration that is also sensitive to lithography failure modes and takes advantage of the large field of view (LFoV) e-beam inspection, is presented. To improve the coverage of the OPC model and the accuracy of the after development inspection (ADI) pattern hotspots prediction - such as trench pinching or bridging in complex 2D routing patterns - a new sampling plan with additional hotpot locations and the corresponding contours input data is introduced. The preliminary inspected hotspots can be added to the traditional OPC modeling flow in order to provide extra information for a hotspot aware OPC model. A compact optical/resist 3D modeling toolkit is applied to interpret the impact of photoresist (PR) profiles, as well as accurate predictions of hotspot patterns occurring at the top or bottom of the PR. A contour-based modeling flow is also introduced that uses a site or edge based calibration engine, to better describe hotspot locations in the hotspot aware OPC model calibration. To quantify the improvement in pattern coverage in the modeling flow, feature vectors (FVs) analysis and comparisons between the conventional and the hotspot aware OPC models is also presented.[1] The time and cost of using conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure such a large amount of CD gauges are prohibitive. By contrast, using LFoV e-beam inspection with improved training algorithm to extract fine contours from wafer hotspots, a hotspot aware OPC model can predict ADI hotspots with a higher capture rate as compared to main feature OPC model. Presumably, a hotspot-aware modeling flow based on LFoV images/contours not only benefits users by improving the capture rate of the lithography defects, but also brings the advantages to the failure mode analysis for the post-etch stage.
Photon absorption statistics combined with a simple model of resist chemistry triggered by each absorbed photon leads to a family of stochastic models with a Gaussian Random Field deprotection. Two important aspects of such models are discussed. First, the generalizations to stochastic reaction-diffusion models, accounting for the effects of depletion, and to models accounting for both exposure-resist stochastic and other process parameter variations, are presented. Second, several options for the stochastic metrics of EUVL processes, both meaningful and useful for lithographers and fast enough to be applicable to the full chip OPC and verification, are described, and some details of their implementations for the full-chip OPC verification and the results of tests are presented. The relation of one of the introduced stochastic metrics to the stochastic-caused variability of the electrical conductance of vertical interconnects (vias) is explained.
We have previously reported the exact convolution-based analytical solution to the problem of an elastic resist shrinkage during post-exposure baking (PEB). In contrast to the PEB problem, the elastic shrinking during development in general does not admit a strict analytical solution. Here we use a numerical finite element method (FEM) to compare a two-step development/shrinking model to the results of simultaneously solving full set of the development equations with the elastic deformations being accounted for. We also report existence of a strict analytical solution for the shrinking of line and space resist patterns; this constitutes a special 2D shrinking case. The results of analytical and numerical solutions are compared, and are shown to agree. In the final section we formulate novel Elastic Compact Model (ECM) that mechanistically captures shrink-induced biases for the resist walls of arbitrary 2D resist patterns. The model is fast and can be used for the full-chip optical proximity corrections (OPC). The accuracy of ECM is analyzed using typical OPC layouts by comparing to FEM results, rigorous simulations, and SEM measurements.
The methods to calculate the probability of success/failure of EUV lithography (EUVL) processes are presented. The success of an EUVL process is defined as a complete removal of the resist material within one set of designated volumes and a complete retention of the resist material within another set of designated volumes in the resist film. We demonstrate that, under certain assumptions, the probability calculation reduces to the well-known problem of calculation of probability of excursion of a certain Gaussian random field. The methods to calculate the probability of success/failure of a lithographic process are presented, including the Monte-Carlo methods, methods based on factorization of a covariance matrix, methods based on Mahalanobis distance, and the methods using Rice’s formula and its variations. A particular attention is paid to the methods applicable to full chip OPC and OPC verification. The results from the proposed methods are tested in simulations and by comparison with experimental data.
Development of a photoresist is a complex physical process involving solid-to-liquid solution phase transition where a developer solution dissolves a section of a patterned resist. The developer can be selective towards either the exposed region (positive-tone) or the unexposed region (negative-tone). Accurate estimation of the development effects is crucial to the prediction of critical dimension (CD) in lithography simulations. Traditionally, the development effects have been captured by a front-propagation equation (such as Mack model and other similar models), which features a development front with a velocity dependent on the resist’s de-protection level. For a positive-tone development (PTD), due to the aqueous nature of the developer, where an exposed part of resist quickly dissolves when in contact with a developer, such a moving front simulates the development process accurately. However, in case of a negative-tone development (NTD), the rate of reaction and resist contrast is significantly lower than for PTD. Therefore it is important to take into account both the developer’s finite diffusion into resist and its reaction rate with the resist to reliably model the development process. In this paper, we discuss the mathematical model of resist’s development by taking into account the transport phenomena of diffusion and reaction taking place during the development step. The finite-element method is used to solve these reaction-diffusion equations over the non-trivial geometry of a patterned resist. We will analyze the results of reaction-diffusion process in comparison to the front propagation methods. The contribution of different model parameters will be described by studying the development rate for resist’s de-protection level and comparing it to the development rate obtained experimentally. We will briefly discuss the results from three dimensional lithographic patterns, which exhibit strong NTD effects.
Chemically amplified resists undergo various chemical phenomena during the photolithography process such as exposure, post-exposure bake (PEB), and development. These chemical changes induce various stresses causing the deformation of exposed region of photoresist. It is imperative to include these deformations in the modeling of lithographic processes especially for negative tone development (NTD) process, where an exposed and deformed part of the resist stays on the substrate after development.
We use rigorous physical model to express the stresses induced by voids created in resist by evaporation of the protecting species. Finite Element method (FEM) is then used to solve three-dimensional elastic deformation equations for resist during PEB and development. The deformation of resist is studied for both one-dimensional gratings and two-dimensional contact holes with varying pitch and optical doses, and we discuss how different modes of deformation are important to be considered in the lithography simulations in order to reduce the critical dimensions’ (CD) computation error. Finally, we briefly introduce a compact model where Fourier series are used to find the exact analytical solution of elastic deformation equations. The results of compact model are compared with the rigorous FEM solution. The compact model is suitable for full chip lithography simulations due to it being numerically fast operations and results comparable to full-physics rigorous simulations.
In this paper, we present a design technology co-optimization (DTCO) flow to pattern self-aligned via (SAV) using two
masks with grapho-epitaxy of lamella BCP and 193i for sub-7nm design. We show that it is necessary to consider both
metal and via layers at the same time in creating design rules with process variations. Due to lamella DSA’s own
characteristics, it can be easily applied in dense memory or SRAM applications for SAV patterning using traditional
single-material metal hard mask. However, to achieve two-mask SAV solution for logic applications, we need to apply
alternating hard mask in metal to cut lamella DSA patterns without compromising the technology scaling.
Directed Self-Assembly is the method by which a self-assembly polymer is forced to follow a desired geometry defined or influenced by a guiding pattern. Such guiding pattern uses surface potentials, confinement or both to achieve polymer configurations that result in circuit-relevant topologies, which can be patterned onto a substrate.
Chemo, and grapho epitaxy of lines and space structures are now routinely inspected at full wafer level to understand the defectivity limits of the materials and their maximum resolution. In the same manner, there is a deeper understanding about the formation of cylinders using grapho-epitaxy processes. Academia has also contributed by developing methods that help reduce the number of masks in advanced nodes by “combining” DSA-compatible groups, thus reducing the total cost of the process.
From the point of view of EDA, new tools are required when a technology is adopted, and most technologies are adopted when they show a clear cost-benefit over alternative techniques. In addition, years of EDA development have led to the creation of very flexible toolkits that permit rapid prototyping and evaluation of new process alternatives. With the development of high-chi materials, and by moving away of the well characterized PS-PMMA systems, as well as novel integrations in the substrates that work in tandem with diblock copolymer systems, it is necessary to assess any new requirements that may or may not need custom tools to support such processes.
Hybrid DSA processes (which contain both chemo and grapho elements), are currently being investigated as possible contenders for sub-5nm process techniques. Because such processes permit the re-distribution of discontinuities in the regular arrays between the substrate and a cut operation, they have the potential to extend the number of applications for DSA.
This paper illustrates the reason as to why some DSA processes can be supported by existing rules and technology, while other processes require the development of highly customized correction tools and models. It also illustrates how developing DSA cannot be done in isolation, and it requires the full collaboration of EDA, Material’s suppliers, Manufacturing equipment, Metrology, and electronic manufacturers.
We present a directed self-assembly (DSA) compliant flow for contact/via layers with immersion lithography assuming the graphoepitaxy process for the cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use template error enhancement factor to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data show that it is promising to achieve two-mask solution with DSA for the contact/via layer using 193i at 5 nm node.
In this paper, we present a DSA compliant flow for contact/via layers with immersion lithography assuming the grapho-epitaxy process for cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use Template Error Enhancement Factor (TEEF) to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data shows that it is promising to achieve 2-mask solution with DSA for the contact/via layer using 193i at 5nm node.
This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.
Directed self-assembly (DSA) patterning has been increasingly investigated as an alternative lithographic process for
future technology nodes. One of the critical specs for DSA patterning is defects generated through annealing process or
by roughness of pre-patterned structure. Due to their high sensitivity to the process and wafer conditions, however,
characterization of those defects still remain challenging.
DSA simulations can be a powerful tool to predict the formation of the DSA defects. In this work, we propose a new
method to perform parallel computing of DSA Monte Carlo (MC) simulations. A consumer graphics card was used to
access its hundreds of processing units for parallel computing. By partitioning the simulation system into non-interacting
domains, we were able to run MC trial moves in parallel on multiple graphics-processing units (GPUs). Our results show
a significant improvement in computational performance.
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