A pulse oximeter is an optical device that monitors tissue oxygenation levels. Traditionally, these devices estimate the oxygenation level by measuring the intensity of the transmitted light through the tissue and are embedded into everyday devices such as smartphones and smartwatches. However, these sensors require prior information and are susceptible to unwanted changes in the intensity, including ambient light, skin tone, and motion artefacts. Previous experiments have shown the potential of Time-of-Flight (ToF) techniques in measurements of tissue hemodynamics. Our proposed technology uses histograms of photon flight paths within the tissue to obtain tissue oxygenation, regardless of the changes in the intensity of the source. Our device is based on a 45ps time-to-digital converter (TDC) which is implemented in a Xilinx Zynq UltraScale+ field programmable gate array (FPGA), a CMOS Single Photon Avalanche Diode (SPAD) detector, and a low-cost compact laser source. All these components including the SPAD detector are manufactured using the latest commercially available technology, which leads to increased linearity, accuracy, and stability for ToF measurements. This proof-of-concept system is approximately 10cm×8cm×5cm in size, with a high potential for shrinkage through further system development and component integration. We demonstrate preliminary results of ToF pulse measurements and report the engineering details, trade-offs, and challenges of this design. We discuss the potential for mass adoption of ToF based pulse oximeters in everyday devices such as smartphones and wearables.
We have built a HOE-based display capable of reconstructing arbitrary images, in mid-air at fixed focal depths, that can interact with the viewer in real-time. The display system comprises the HOE, a laser projection subsystem, a Kinect motion sensor and an embedded controller. The HOE functions as a fast converging lens and is A4 page sized (20×30cm). We have written a number of simple apps for the display that allow the user to draw in mid-air or to touch icons and buttons that trigger other actions. The reconstructed holographic images are high-resolution, relatively bright and visible under ambient indoor lighting conditions.
A simple low resolution volumetric display is presented, based on holographic volume-segments. The display system
comprises a proprietary holographic screen, laser projector, associated optics plus a control unit. The holographic screen
resembles a sheet of frosted glass about A4 in size (20x30cm). The holographic screen is rear-illuminated by the laser
projector, which is in turn driven by the controller, to produce simple 3D images that appear outside the plane of the
screen. A series of spatially multiplexed and interleaved interference patterns are pre-encoded across the surface of the
holographic screen. Each illumination pattern is capable of reconstructing a single holographic volume-segment. Up to
nine holograms are multiplexed on the holographic screen in a variety of configurations including a series of numeric
and segmented digits. The demonstrator has good results under laboratory conditions with moving colour 3D images in
front of or behind the holographic screen.
Microdisplays are used in many applications from electronic viewfinders to rear projection television and even in non-display applications such as printers. There exist a number of microdisplay technologies based upon different materials and physical systems. We outline the various classes of microdisplay along with their suitability for certain applications. We describe an emerging microdisplay technology based on a combination of polymeric organic electroluminescent material and CMOS active-matrix backplane, making comparisons with conventional OLED display technology and other microdisplay technologies. We focus, in particular, on a novel active matrix addressing approach for the emerging technology.
A new hybrid optoelectronic technology has been developed which utilizes a very thin layer of light emitting polymer material on a CMOS silicon active-matrix substrate to create a 2-D array of independently programmable optical emitters. The technology has been developed thus far primarily for its use as a microdisplay. Here we detail aspects of device design and characterization. We consider the relevance of the new technology to optical and photonic systems other than displays.
This paper presents the development of an electrical SPICE model of a Ferroelectric Liquid Crystal (FLC) on silicon microdisplay. Previous work has investigated the use of an electro-optical SPICE model to simulate the optical response of an FLC cell to a given electrical signal. However, the design of the backplane drive scheme for the display also requires an accurate model of the electrical load represented by an FLC cell. The model presented here provides a good fit to electrical measurement results and, in addition, can be combined with elements of the electro-optical model to allow the optical response of the cell to be modelled at the same time. This paper also presents results of charge collection current measurements which highlight the differences in the behavior of the cell when it is switched between positive and negative voltages and then in the other direction.
Tristate antiferroelectric and v-shaped liquid crystal materials have recently offered the promise of both the fast switching of ferroelectric materials and the analogue switching of nematic materials at drive voltages compatible with those available from standard CMOS technology thereby making them, at least in principle, suitable for consideration in microdisplay and other photonic applications. AFLC development is in its early stages and the materials are not yet mature enough for widespread commercial use. The object of the ESPRIT funded MINDIS project has been to evaluate AF-LCoS technology. The electro-optical characteristics of a number of experimental materials have been experimentally measured in test cells that emulate the situation of a silicon backplane (e.g., aluminum reflective back electrode etc). Some candidate materials been shown to exhibit high contrast, uniformity and repeatability. A CMOS active matrix backplane with 1000 line resolution has been designed and fabricated. The backplane is capable of operating in digital or analogue modes for FLC and AFLC respectively. Planarization techniques have been applied to the CMOS wafers but planarization has been shown to be more problematic than with previous backplanes. The reasons for this are discussed. The technology has been theoretically evaluated for use in microdisplays for both projection and near-to-eye applications.
Optimal performance of a Liquid Crystal on Silicon (LCoS) device requires an integrated approach incorporating both optical and electrical design elements. In particular, during the design of both the IC back plane and the voltage waveforms used to drive fast switching Ferroelectric LC (FLC) the electro-optical properties of the LC must be considered to ensure that the best use is made of the FLC. Although, SPICE equivalent circuits for FLC materials have been developed and can be used for this purpose their accuracy relies upon the measurement of a number of parameters. Unfortunately, the accuracy of measuring key parameters is often poor, resulting in a relatively large margin of error in the final model. However, this need not be the case. In this paper we present a methodology which uses standard IC parameter extraction software to simulate and optimize the FLC SPICE model parameters such that the model closely matches the measured response of the sample. By using this approach we identify a set of parameters which when combined provide a SPICE equivalent circuit which models the FLC repsonse to a given input waveform.
Defect free homogeneous alignment of ferroelectric liquid crystals in the surface stabilized configuration remains challenging to obtain even over the relatively small area of liquid crystal on silicon microdisplays. The limitations of the conventional rubbed polymer alignment technique are discussed and the benefits brought by recent advances in backplane post-processing are demonstrated in realistic conditions. The potential of the linearly photopolymerized photoalignment technique are highlighted in terms of alignment quality, susceptibility to zigzag defects, and electro-optical performances.
In this paper we describe the development of a CMOS VLSI backplane for use with micromachined silicon nitride membrane mirrors. The backplane consists of an array of 4096 pixels which are addressed by a 6-bit row decoder. Data enters the chip as a 64-bit logic word at standard CMOS 0-5V levels and is converted to 0-50V at the pixel level by an optimized cascade voltage switch logic circuit.
Liquid-crystal over silicon is an established technology for reflective spatial light modulators and microdisplays. This paper reviews their development to date, highlighting in particular the micromachining of the mirror array and the associated packaging issues.
Liquid crystal over silicon (LCoS) is an established technology for reflective spatial light modulators (SLM's) and microdisplays. While most of the manufacturing methods used are mature, there exist a number of unresolved issues associated with the mass production of high quality devices. Existing manufacturing technology leaves the final mirror elements raised from the surface of the surrounding dielectric causing problems with the filling of the liquid crystal (LC). The flow front during filling is influential on the final alignment qualities, so it is essential that this flow front follows the ideal linear shape. We report on a method to remove this mirror step height by the use of an aluminum dual damascene technique. This process produces mirrors which are embedded within the dielectric insulating layer thereby removing most of the LC flow front aberrations, caused by the surface topography, during LC filling. We discuss the novel methods developed to overcome the damascene induced problems of dishing and erosion. The results will be discussed with particular bias towards their use in the manufacture of reflective micro-displays.
This paper compares the performance of quadratic and covariance models for a RESURF device. TCAD is used in conjunction with a CCI design and both response surfaces and response variances are compared for both models. Experimentally measured distributions are compared with those predicted by TCAD and the differences used to help identify other possible sources of variation.
The alignment of ferroelectric liquid crystal (FLC) is heavily influenced by the FLC flow rate during SLM cell filling. This flow rate is affected by a number of factors, one aspect of which is the structure of the silicon backplane. Even when the device has been planarized the structure of the pixelated top layer metal still influences the FLC flow rate and therefore the FLC alignment. We have produced a flat silicon backplane substrate using damascene processing to manufacture the mirror/electrodes. Damascene processing is a metal polishing technique. In this process the oxide layer which has already been polished is etched to create trenches in the desired pattern of the metal layer, a blanket deposition of metal is then performed, which fills the trenches and covers the wafer surface, finally CMP is performed, which removes the excess material on the wafer surface leaving the metal in the trenches and the top surface flat. There are some problems associated with damascene processing which will affect its suitability in the micro-=fabrication of SLM backplanes. The softer metal material is prone to dishing and scratching and the harder oxide material can be eroded. THese effects are dependent on the level of control of the CMP process. A process is being developed, using novel slurry chemistries, to allow the incorporation of this technique into our post-processing procedure. The results of the application of this process to test structures and an analysis of the suitability of this technique in the microfabrication of SLM silicon backplanes will be presented.
The structure and principle of operation of a ferroelectric liquid crystal - over - CMOS silicon display are described. Several addressing schemes for creating full color images are introduced and assessed. Preliminary results using 176 X 176 pixel and 512 X 512 pixel DRAM displays are presented.
Ferroelectric liquid crystal over VLSI silicon spatial light modulators have been successfully employed as input and filter devices in optical correlator architectures for image processing and target recognition. A considerable limitation of these systems is their difficulty in extracting the desired target from clutter, particularly where this clutter has similar characteristics to the target. We present a novel set of image processing techniques for improving the target to clutter ratio, thereby simplifying the task of achieving correct target recognition. A stereo-pair of images captured from the input scene is enhanced using morphological image processing functions implemented as convolutions with an output threshold. Stereo pairs allow extraction of regions of interest based upon range. These regions are automatically extracted from the enhanced images ready for target recognition via a conventional correlation function. The clutter reduction algorithm does not require a priori knowledge of the target and so is a robust method for target recognition. All of the functions used can be expressed in terms of correlations and convolutions with an output threshold, allowing implementation on a correlator processing architecture. Initial experimental results from a Vanderlugt 4f optical correlator utilizing SLMs 256 by 256 pixel at the input and filter planes are presented. These results are compared to those from computer simulations and the performance of the optical system is assessed.
Full color images have been demonstrated on a high frame rate, binary, ferroelectric liquid crystal (FLC) display or spatial light modulator (SLM). This display consists of binary surface stabilized ferroelectric liquid (SSFLC) crystal over a custom foundry CMOS silicon VLSI (FLC/VLSI) backplane and provides a new alternative to current well established display technologies. Many issues have been considered to enhance the optical quality of these displays such as the post-processing of the foundry silicon to achieve a high optical flatness and pixel fill factor; with improved liquid crystal alignment. Optimization of electrical addressing schemes and color illumination for video display purposes have been investigated resulting in recommendations for future developments.
Liquid crystal (LC) over silicon backplane spatial light modulators (SLMs) have applications in optical processing and as miniature displays. With these devices a LC layer is sandwiched between the silicon backplane and a front cover glass coated with a transparent ITO electrode. The voltage between electrodes on the controlling circuitry and the ITO electrode determines the state of the LC which in turn is used to modulate incident light onto the device. The silicon backplane consists of an array of pixels similar to DRAM or SRAM devices but where each pixel controls the voltage on an electrode. These electrodes must also act as mirrors reflecting the incident light. The silicon backplanes supplied by commercial foundries which work well electrically suffer from having poor optical quality pixel mirrors. These mirrors have inferior surface quality with low flat fill factor resulting in low optical efficiency. Hillocks are also present which cause problems with LC cell construction. We have developed a post-processing procedure based on silicon microfabrication techniques to add another level of metal to commercially fabricated wafers which addresses these problems. To ensure that his new metal layer is deposited onto a very flat substrate the interlevel dielectric is planarized using chemical mechanical polishing. We have developed this technique to produce an optical quality surface with local surface variations of less than 100 angstrom consistently achieved. The deposited aluminium top layer is optimized for best optical performance within the constraints of the electrical characteristics. Pixel mirrors with flat fill factors up to 84% were realized which improved the optical efficiency of the SLM. No hillocks were present on the metal surface presenting the opportunity to fabricate 1 micrometers thick LC cells to fully utilize the potential of ferroelectric LC. We will also report on a n expansion of the post-processing procedure to protect devices based on DRAM memory layout from photo induced charge leakage. The use of microfabrication techniques to construct the LC spacer layer will also be discussed.
We describe a new technology which is appropriate for the production of lightweight, highly compact displays. It is based upon a thin layer of ferroelectric liquid crystal (FLC) on top of, and directly driven by, an active matrix backplane fabricated on single crystal silicon. While devices can be produced using fairly standard techniques, we have developed custon fabrication and packaging techniques, required for optimization of optical quality and performance. We have successfully developed the technology for spatial light modulators for use in applications such as optical correlators and programmable holograms. The FLC is configured in the binary surface stabilized configuration: the CMOS circuits are digital in nature. The device operates in reflection with each pixel having an aluminium pad which acts as a mirror to reflect light and as an electorde to control the state of the overlying FLC. The technology also shows promise as a display technology so we have demonstrated the devices as displays capable of displaying both grey scale and color. We have built FLC devices upon commercially fabricated wafers but have found it advantageous to carry out custom post processing order to improve performance. The main thrust to date has been the use of ECR oxide deposition followed by chemical mechanical polishing to provide an optically flat substrate for mirror deposition. This allows the deposition of flat mirrors which fill almost all of the pixel area; it also allows optimization of the mirror deposition for high optical quality and good FLC alignment. Work is also well advanced on a technique to fill the vias connecting to the mirror layer and on packaging devices to reduce bowing of the silicon and increase the thickness uniformity of the FLC layer. Recent results are demonstrated on LCDs fabricated above two silicon backplanes containing 176 X 176 pixels and 256 X 256 pixels respectively, the former having dynamic signal storage at each pixel, the latter static storage.
There is a growing requirement for helmet or head mounted display systems that can deliver task-specific information direct to the user on a personal basis. The complexity of this information (and consequently that of the display) can range from simple status indicators through to high quality video. In this paper, we review three miniature display technologies which have been, or are being developed by GEC-Marconi for helmet or head mounted applications. These are light emitting diodes (LEDs), DC thin film electroluminescent displays and ferroelectric liquid crystal over CMOS silicon. The current development status of each of these technologies is reviewed and some of the factors governing the choice of a particular technology discussed.
Ian Underwood, David Vass, Richard Sillitto, George Bradford, Norman Fancey, Adil Al-Chalabi, Martin Birch, William Crossland, Adrian Sparks, Steve Latham
The development of a ferroelectric liquid-crystal-over-single-crystal-silicon spatial light modulator is described. The reflective SLM has an array of 176 X 176 pixels over a clear aperture of 5.28 mm X 5.28 mm. Prototype devices driven from a specially designed high speed frame store have been operated at frame rates of approximately equals 1 kHz.
The new high performance liquid crystal over silicon spatial light modulators allows fast electrical modulation, however, such SLMs are binary and pixelated, typically with a small pixel fill factor. This paper investigates the usefulness of these devices as Fourier components, both for optical filtering and as electrically addressed Fourier holographic elements.
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