KEYWORDS: Defect detection, Inspection, Transmission electron microscopy, Signal detection, Sensors, Semiconducting wafers, Scanning electron microscopy, Defect inspection, Data storage
A high-throughput e-beam monitoring strategy was developed for capturing advanced DRAM storage node (SN) defects after etching process, when high-aspect-ratio (HAR) structure is involved. With this novel approach, two types of defects, SN-bowing-short and SN-open, were captured with solid signatures. In this study, two wafers with the same structure at different technology nodes,1A and 1B, were used. To enhance the defects signal, back scattered electron (BSE) mode was used to enhance the material contrast for the bottom of HAR holes. With improved BSE image quality, SN-bowing short type was caught using defect detection based on traditional array mode detection. SN-open, however, is more challenging because of its smaller dimension and HAR, resulting in an extremely narrow detection window of image gray level difference between normal storage node hole and the defective one. In order to capture this type of defect, an die-to-database (D2DB) comparison system for e-Beam inspection was applied to address this critical defect and its wafer signature was revealed with extremely high throughput and sensitivity.
With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
The mask is a known contributor to intra-field and local patterning fingerprints at the wafer level. Traditionally, a 3σ distribution of critical dimensions (CDs) on mask was sufficient to characterize the contribution to the CD distribution at wafer level. However, as edge placement error (EPE) and EUV wafer patterning stochastics become critical with decreasing feature sizes, wafer CD distributions are being characterized for statistics beyond 3σ. Additionally, Local Placement Error (LPE) is a critical metric that is expected to contribute to EPE. Consequently, it is imperative to understand, characterize and control the EUV mask contributors to the EPE budget. This work is an attempt to extensively characterize the CD and LPE distribution on an EUV mask and identify its impact at wafer level.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.