KEYWORDS: Statistical modeling, Data modeling, Transistors, Semiconducting wafers, Monte Carlo methods, Optimization (mathematics), Performance modeling, Process modeling, Device simulation, Manufacturing
Variability modeling at the compact transistor model level can enable statistically optimized designs in
view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware
compact model characterization methodology based on the linear propagation of variance. Hierarchical
spatial variability patterns of selected compact model parameters are directly calculated from transistor array
test structures. This methodology has been implemented and tested using transistor I-V measurements and the
EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter
extractions. Further studies are done on the proper selection of both compact model parameters and electrical
measurement metrics used in the method.
Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits
are described. These results are from multi-discipline, collaborative university-industry research and emphasize
anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes
design and testing electronic monitors in silicon at 45 nm and
fast-CAD tools to identify systematic variations for entire
chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress
random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the
presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and
speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow
characterization.
We have previously analyzed spatial process variation using 45nm ring oscillator arrays. Our hierarchical variability
model had proven to be very useful in revealing interesting systematic patterns, and in separating them from native
random variability. To further understand the underlying mechanism of the process variation, we continue to work on the
analysis and modeling of spatial variation of transistors made on the same 45nm technology test chips. A novel statistical
compact device modeling procedure is used to extract the systematic and random variation of device parameters across
wafer and within die. Statistical SPICE simulation is then performed based on the extracted variation model of device
parameters. The results compare well with actual ring oscillator and SRAM measurements, in that the characteristic systematic, spatial and random patterns have been captured for circuit-level simulation.
In previous publications we have proposed a hierarchical variability model and verified it with 90nm test data. This
model is now validated with a new set of 45nm test chips. A mixed sampling scheme with both sparse and exhaustive
measurements is designed to capture both wafer level and chip level variations. Statistical analysis shows that the acrosswafer
systematic function can be sufficiently described as parabolic, while the within-die systematic variation is now
very small, with no discernible systematic component. Analysis of pattern dependent effects on leakage current shows
that systematic pattern-to-pattern LEFF variation is almost eliminated by optical proximity correction (OPC), but stressrelated
variation is not. Intentionally introduced gate length offset between two wafers in our dataset provides insight to
device parameter variability and sheds additional light on the underlying sources of process variation.
As technologies scale, the impact of process variations to circuit performance and power consumption is increasingly
significant. In order to improve the efficiency of statistical circuit optimization, a better understanding of the relationship
between circuit variability and process variation is needed. Our work proposes a hierarchical variability model, which
addresses both systematic and random variations at wafer, field, die, and device level, and spatial correlation artifacts are
captured implicitly. Finally, layout dependent effects are incorporated as an additive component. The model is verified
by applying to 90nm ring oscillator measurement data and can be used for variability prediction and optimization.
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