KEYWORDS: Semiconducting wafers, Metals, Back end of line, Silver, Optical lithography, Transmission electron microscopy, Nanosheets, Front end of line, Wafer bonding, Semiconductors
The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.