As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.
Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last
decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly
important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon
engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire
field through process windows. LMC is catching and reporting weak lithographic points having small process windows
or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters.
ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can
be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at
different field locations. In this study we compare such across-field LMC verification with a reference LMC without any
scanner specific data.
Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various
across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots
or scanner drifts and compared with wafer measurement.
Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the
impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the
methodology on identified critical hot spots.
Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela CanvasTM GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.
Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in
the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has
penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability
concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires
simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely
hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and
troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples
of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated
environment.
As the semiconductor industry goes into the 65nm generation, designs become more complex, mask cost increases exponentially, and the industry is pushing very hard on the lithography process. It is more and more challenging to achieve and maintain acceptable yield. Yield is not only a problem for the Fabs but also an issue that has to be considered by the chip designers. In order to save turn around time, save mask and process development cost and improve the yield, the lithography problems need to be resolved at the design stage. The designers need to be aware of the lithography behavior of their design and be able to modify the design if it causes yield problems in the lithography process.
In this paper, we discuss a new tool, a Litho Yield Checker, which can be run stand-alone but is also fully integrated with a Layout Editor, that provides its user with an easy way to visualize how the layouts are to be printed on wafer, and see the common process window (CPW) for the most important locations in the design.
Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, “Mask” issues have emerged as one of the main production problems due to their rising cost and long turn-around time. Mask-making specifications related to defects found on advanced masks also becomes more difficult to define due to the complex features involved [e.g. OPC (Optical Proximity Correction), SRAF (Sub Resolution Assist Features), etc.]. The Automatic Defect Severity Scoring (ADSS) module of i-Virtual Stepper System from Synopsys offers a fast and highly accurate software solution for defect printability analysis of advanced masks in a real production environment. In this paper, we present our case study of production pilot run in which the ADSS is used to automatically quantify the impact of a given defect on the surrounding features, basically filtering out killer defects and nuisance defects in terms of production viewpoints to reduce operators’ intervention. In addition, an automation workflow is also tested, in which the production issues, such as the communication feasibility of mask quality control between mask house and wafer fab, are also considered.
As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects get more and more severe. As such, aggressive Optical Proximity Correction (OPC) features like hammerheads, serifs and assist bars inevitably appear on fabricated masks. The great challenge, however -- to reliably assure the quality of these advanced masks -- is to be able to directly judge a controversial defect under such complex features. It is necessary to find a more effective way to accurately disposition the defects found on these masks. Simulation-based defect disposition strategies have now become much more important for judging defect printability. In this paper, we will study and characterize the printability prediction of various defects on high-end masks by Virtual Stepper® System with its improved Automated Defect Severity Scoring (ADSSTM) function. Both line-space masks with aggressive OPC features like assist bars and attenuated PSM with contact features with small sizes were used to verify the simulation engine and ADSS algorithm in this study. The Virtual Stepper simulation and defect impact analysis results (the automatically calculated Defect Severity Score) will be compared to the SEM images and measurements of wafer prints using 248nm lithography. In addition, production reticles are also used to compare the accuracy and efficiency of ADSS with human review. A new defect disposition flow is also tentatively proposed here to demonstrate that the Virtual Stepper System with its ADSS feature can provide its user with an automated, fast and accurate way of analyzing the impact of a defect. The Virtual Stepper System with ADSS function has been shown to be a suitable tool for photomask defect criticality assessment in mask shops and wafer fabs.
Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, the traditional mask defect analysis method becomes very time consuming. The Automatic Defect Severity Scoring (ADSS) module of i-Virtual Stepper System from Numerical Technologies offers an extremely fast and highly accurate software solution for defect printability analysis of advanced masks such as OPC and phase-shifting masks in a real production environment. In a previous paper [1], we have introduced the ADSS concept and discussed some results for line-space patterns on OPC and non-OPC masks. In this paper, we will discuss the ADSS results for both line-space and contact patterns on attenuated phase-shifting masks (ATTPSM), together with some ADSS results for line-space patterns on binary masks. The ADSS results are compared to wafer results. The wafer exposures were performed using 248 nm imaging technology and inspection images were generated on a KLA-Tencor’s SLF27 system.
In this paper the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repaired binary masks are performed by Virtual Stepper System in a real production environment. In addition, the Automatic Defect Severity Scoring module in Virtual Stepper is also used to calculate the defect severity score for each defect. ADSS provides an overall score that quantifies the impact of a given defect on the surrounding features. For the binary masks, the quality of reported defects is studied. For the ATTPSM three types of programmed defects on both line/space and contact hole patterns are assessed. Wafer exposures are performed using 248 nm imaging technology and inspection images generated on a KLA-Tencor's SLF27 system. These images are used by the Virtual Stepper System to simulate wafer images under the specific stepper parameters. The result are compared to SEM images of resist patterns and Aerial Image Measurement System simulated results.
Sub-wavelength lithography requires knowledgeable application of resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift mask (PSM). Use of RETs, in turn, requires that new photomask specifications and special requirements for mask defect printability be taken into consideration. This is especially true, as the photomask's critical dimensions become more aggressive (400 nm moving toward 300 nm). Traditionally, mask defect analysis and subsequent defect disposition has been accomplished by first performing automated reticle inspection, and then by visual inspection ultimately dependent on operator judgement. As the semiconductor industry moves to more challenging process generations this methodology is no longer viable for assessing the impact of a defect on the printed wafer. New techniques for more accurate, production-worthy defect printability analysis and defect disposition procedures are required. Developed at Numerical Technologies, Inc. is the Virtual StepperTM System that offers a fast, accurate software solution for defect printability analysis based on state-of- the-art lithography simulation techniques for advanced masks production using OPC and PSM. The newly developed Virtual Stepper System feature, Automatic Defect Severity Scoring (ADSS) provides fully automated and accurate defect impact analysis capability by calculating a consistent Defect Severity Score (DSS) for each defect detected by an inspection tool. DSS is an overall score that quantifies the impact of a given defect on surrounding features and can be used as a comprehensive indicator of defect printability. Taken into consideration, are not only printing defects, but defects which cause critical dimension (CD) errors altering a given process window.
As Optical Proximity Correction (OPC0 and Phase Shifting (PSM) become more and more commonly used for producing smaller features on wafer, the photomask (reticle) manufacturing, that is mask writing, inspection and repairing, and quality assurance become more challenging for both mask shops and wafer fabs. Consequently, a powerful defect analysis tool is needed to determine which defect is a nuisance defect, which defect needs to be repaired, and how good is the repair. It should have the capability for defect printability prediction and analysis of defect impact on device performance. In this paper, we will study and characterize the printability prediction of programmed defects on binary OPC masks by the Virtual Stepper System with its newly developed Automated Defect Severity Scoring (ADSS) function. AMD's defect test reticles HellOPC2 were used. The Virtual Stepper simulation and defect impact analysis results (the automatically calculated Defect Severity Score) will be compared to the SEM images and measurements of wafer prints using 193nm lithography. The results demonstrate that the Virtual Stepper System with its ADSS feature can provide its user with an automate, fast and accurate way of analyzing the impact of a defect. The Virtual Stepper System with ADSS function will be a suitable tool for photomask defect critically assessment in mask shops and wafer fabs.
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