The semiconductor industry has been largely using the mean+3sigma overlay dispositioning metric for over 20 years now. As technology shrink progresses, this metric does not represent the most accurate overlay condition on the wafer. The continuous usage of the traditional metric leads to non-optimal rework decisions and potential yield loss in high-volume manufacturing (HVM). We propose an alternative overlay dispositioning metric that reduces rework without compromising accuracy or sampling. The proposed metric is called ‘number-of-dies-within-spec’. It is obtained by first evaluating the overlay model on a dense grid, followed by comparing the grid values against the spec limits. Based on that, each die can be evaluated, and dies below the spec are counted to obtain the wafer key performance indicator (KPI) “number-of-dies-within-spec”. This paper shows the rework gain for two layers when using our proposed metric against the traditional mean+3sigma dispositioning.
In this paper we present a powerful virtual metrology system to aid in-fab product lot level dispositioning and yield learning. CD and overlay measurement data of different layers are modeled across the wafers and mapped to dense dose, focus, and overlay grids. These are input processing conditions for design-specific computational lithography to predict on full-wafer, full-chip inter-layer overlap area and critical edge-to-edge distances, which are thereafter used to predict electrical failure. The system is composed of an off-line inter-layer hotspot database and an on-line real time dispositioning module. It supports complex multi-patterning stacks with or without self-aligned processes. Example runs have been conducted for 14 nm node metal and via layers, using both FEM-like and typical nominal production wafer data, and the results are as expected from lithographical point of view. Comparing with traditional wafer dispositioning based on static overlay spec and CD spec, our system outputs wafer map stacked with failed dies locations, worst case hotspots contours, root cause analysis, list of worst hotspots and worst dies for inspection, and help litho engineer make an educated decision on wafer dispositioning. This will help fab optimize CD – Overlay process window, improve yield ramp, reduce wafer rework rate, and hence reduce cost, and shorten turn-around-time. The system’s computation is fast and inline real time wafer dispositioning aided by computational lithography is made possible by the system.
Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.
Dual damascene is an established patterning process for back-end-of-line to generate copper interconnects and lines. One of the critical output parameters is the electrical resistance of the metal lines. In our 200 mm line, this is currently being controlled by a feed-forward control from the etch process to the final step in the CMP process. In this paper, we investigate the impact of alternative feed-forward control using a calibrated physical model that estimates the impact on electrical resistance of the metal lines* . This is done by simulation on a large set of wafers. Three different approaches are evaluated, one of which uses different feed-forward settings for different radial zones in the CMP process.
In a 200 mm high volume environment, we studied data from a dual damascene process. Dual damascene is a combination of lithography, etch and CMP that is used to create copper lines and contacts in one single step. During these process steps, different metal CD are measured by different measurement methods. In this study, we analyze the key numbers of the different measurements after different process steps and develop simple models to predict the electrical behavior* . In addition, radial profiles have been analyzed of both inline measurement parameters and electrical parameters. A matching method was developed based on inline and electrical data. Finally, correlation analysis for radial signatures is presented that can be used to predict excursions in electrical signatures.
After critical lithography steps, overlay and CD are measured to determine if the wafers need to be re-worked. Traditionally, overlay metrics are applied per X/Y-direction and, a CD metric is computed independently. From design standpoint, electrical failure is based on a complex interaction between CD deviations and overlay errors. We propose a method including design constraints, where results of different measurement steps are not judged individually, but in a combined way. We illustrate this with a critical design feature consisting of a contact requiring minimum distance to a neighboring metal line, resulting in much better correlation to yield than traditional methods.
Electron optics can assist in the fabrication of semiconductor devices in many challenges that arise from the ongoing decrease of structure size. Examples are augmenting optical lithography by electron beam direct write strategies and high-throughput imaging of patterned structures with multiple beam electron microscopes. We use multiple beam electron microscopy to image semiconductor wafers processed by electron beam lithography.
KEYWORDS: Metals, Semiconducting wafers, Electron beam lithography, Etching, Electron beam direct write lithography, Photomasks, Optical alignment, Wafer-level optics, Back end of line, Electron beams
Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks.
However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today’s single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3].
Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level.
In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.
KEYWORDS: Metals, Etching, Semiconducting wafers, Optical alignment, Electron beam direct write lithography, Photomasks, Back end of line, Electron beam lithography, Scanning electron microscopy, Electron beams
Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho – etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.
KEYWORDS: Back end of line, Transistors, Semiconducting wafers, Dielectrics, Oxides, Resistance, Copper, Electron beam lithography, Capacitance, Metals
While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct
patterning is still being considered as an alternative or complementary approach for patterning of advanced technology
nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new
challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in
the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore,
degradation of product reliability may occur. These questions have not yet been clarified in detail.
For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels
using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to
non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the
typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits,
suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a
decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes.
In electron proximity effect correction (PEC), the quality of a correction is highly dependent on the quality of the model.
Therefore it is of primary importance to have a reliable methodology to extract the parameters and assess the quality of a
model. Among others the model describes how the energy of the electrons spreads out in the target material (via the
Point Spread Function, PSF) as well as the influence of the resist process. There are different models available in
previous studies, as well as several different approaches to obtain the appropriate value for their parameters. However,
those are restricted in terms of complexity, or require a prohibitive number of measurements, which is limited for a
certain PSF model.
In this work, we propose a straightforward approach to obtain the value of parameters of a PSF. The methodology is
general enough to apply for more sophisticated models as well. It focused on improving the three steps of model
calibration procedure: First, it is using a good set of calibration patterns. Secondly, it secures the optimization step and
avoids falling into a local optimum. And finally the developed method provides an improved analysis of the calibration
step, which allows quantifying the quality of the model as well as enabling a comparison of different models. The
methodology described in the paper is implemented as specific module in a commercial tool.
Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at
193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS
manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho
can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho-
Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional
(1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data
prep efforts such as layout splitting.
In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm
lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular
lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a
VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic
Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam
resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements
necessary for this mix & match approach will be discussed.
To fulfill the requirements of future technology nodes new resists with high resolution, high sensitivity and low
LWR and LER respectively are needed. A new inorganic non-chemically amplified resist (XE15IB, an experimental
resist provided by Inpria Corp.) was investigated. The resist is spin-cast from aqueous solution and is
based on hafnium oxide. Metal oxide based resist as XE15IB supersede other resist materials due to its high
etch resistance.1, 2 This new material can be considered as a direct patternable spin on hard mask.
XE15IB was processed in a 300mm complementary metal oxide semiconductor (CMOS) manufacturing environment
and exposed on a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer
Center Nanoelectronic Technologies (CNT).
The resist was evaluated in terms of contrast, sensitivity and resolution. The process characteristics required
for CMOS manufacturing such as delay stability were also examined. Furthermore, by printing a large static
random access Memory (SRAM) pattern (design CD of 22 nm), the exposure of a real application pattern was
demonstrated.
A new correction approach was developed to improve the process window of electron beam lithography and push its
resolution at least one generation further using the same exposure tool. An efficient combination of dose and geometry
modulation is implemented in the commercial data preparation software, called Inscale®, from Aselta Nanographics.
Furthermore, the electron Resolution Improvement Feature (eRIF) is tested, which is based on the dose modulation and
multiple-pass exposure, for not only overcoming the narrow resist process windows and disability of exposure tool but
also more accurate correction of exposure data in the application of sub-35nm regime. Firstly, we are demonstrating the
newly developed correction method through the comparison of its test exposure and the one with conventional dose
modulation method. Secondly, the electron Resolution Improvement Feature is presented with the test application for
complementary exposure and with the application of real design, specifically for sub-30nm nodes. Finally, we discuss
the requirements of data preparation for the practical applications in e-beam lithography, especially for future technology
nodes.
For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face nodes well below a 32-nm half pitch in the next 2 to 3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct-write variable-shaped beam equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a contact to be placed later. Up to now, the control of printed patterns such as line ends was achieved by a proximity effect correction mostly based on a dose modulation. This investigation of line end shortening (LES) includes multiple novel approaches, and contains an additional geometrical correction to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies using its state-of-the-art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production-like pattern in the range of our targeted critical structure dimensions in dense line space features smaller than 40 nm will be shown.
KEYWORDS: Cadmium sulfide, Computer simulations, Semiconducting wafers, Electron beam lithography, Electron beams, Detection and tracking algorithms, Point spread functions, Electron beam direct write lithography, Modulation, Nanoelectronics
For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below
32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with
electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely
reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both
dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later
placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a
proximity effect correction (PEC) which is mostly based on a dose modulation.
This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional
geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The
designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and
measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer
and CD-SEM.
Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large
production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.
Electron Beam Direct Write (EBDW) lithography is used in the IC manufacturing industry to sustain optical
lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop advanced
technologies, ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the
specifications in terms of dimension control and roughness becomes tighter. In addition, the shrink of the size and pitch
of features significantly reduces the process window of lithographic tools. In EBDW, the standard proximity effects
corrections only based on dose modulation show difficulties to provide the required Energy Latitude for patterning
structures designed below 45nm. A new approach is thus needed to improve the process window of EBDW lithography
and push its resolution capabilities.
In previous papers, a new writing strategy based on multiple pass exposure has been introduced and optimized to
pattern critical dense lines. This new technique consists in adding small electron Resolution Improvement Features
(eRIFs) on top of the nominal structures. Then this new design is exposed in two successive passes with optimized doses.
Previous studies were led to evaluate this new writing technique and establish rules to optimize the design of the eRIF.
Significant improvements have already been demonstrated on SRAM and Logic structures down to the 16nm node.
These results were obtained with a tool dedicated to the 45nm node. The next step of this work is thus to automatically
implement the eRIF to correct large-scale layouts.
In this paper, a new data preparation flow is set up for EBDW lithography. It uses the eRIF solution as a full
advanced correction method for critical structures. The specific correction rules established in our previous studies are
implemented to improve the CD control and the patterning of corners and line ends. Moreover, the dose and shape of the
eRIFs are automatically tuned to best fit the nominal design. This work is done with "INSCALE®", the new data
preparation software from ASELTA Nanographics. This data preparation flow is then applied on layouts down to the
22nm node. Comparisons with the standard dose modulation flow demonstrate that adding eRIFs significantly improves
the process window and thus the resolution of e-beam tools. It also shows that the multiple pass exposure technique can
be used as a specific correction method on large scale layouts.
KEYWORDS: Semiconducting wafers, Computer simulations, Cadmium, Modulation, Detection and tracking algorithms, Electron beam lithography, Electron beams, Electron beam direct write lithography, Point spread functions, Nanoelectronics
For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below
32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with
electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely
reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both
dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later
placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a
proximity effect correction (PEC) which is mostly based on a dose modulation.
This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional
geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The
designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and
measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer
and CD-SEM.
Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large
production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.
For current and future semiconductor technology nodes with critical dimensions of 32 nm or below, the e-beam
lithography is faced with increasing challenges to achieve a reasonable patterning of structures, especially if a process
with a chemically amplified resist is used. The reasons for these limitations are the physical properties of the transfer
process used to print a structure onto the resist-coated substrate, which inherently contains an unavoidable blurring of the
deposited e-beam energy around the desired shape. This blurring is usually described by a so called process proximity
function (PPF) and mostly approximated by a superposition of two or more Gaussian functions. The PPF includes the e-beam
blur, electron forward scattering and resist effects (often described altogether by the so called alpha parameter of
the PPF [K. Keil et al, "Resolution and total blur: Correlation and focus-dependencies in e-beam lithography," J. Vac.
Sci. Technol. B 27, 2722 (2009)]) as well as the backscattering effect (often described by the so called beta parameter of
the PPF). When the desired critical dimensions of structures are near or below the alpha parameter of the PPF, depending
on their environment it may be just impossible to print the structures because of the vanishing image contrast. The PPF
model confirms this well-known behavior but also shows ways and limits for improvements.
This paper provides real pattern lithography results - comparing classical and GIDC correction - for exposures done on a
Vistec SB3050DW shaped e-beam writer. A performance comparison of the GIDC method and the classical dose
correction in terms of data preparation and writing time is presented.
The e-beam lithography is faced with increasing challenges to achieve a satisfying patterning of structures with critical dimensions of
about 32 nm or below. The reason for this issue is the unavoidable blurring of the deposited e-beam energy due to beam blur, electron
scattering (forward and backward), and resist effects. The distribution of the finally deposited dose differs from the dose weighted
geometry of the printed layout. In general, the finally deposited dose is described as convolution of the layout with a process specific
proximity function being a model for the unavoidable blurring. This process proximity function (PPF) is often approximated by a
superposition of two or more Gaussian functions. Thus, the electron forward scattering and resist effects, being most critical to the
pattern fidelity, are often described altogether by the so called alpha-parameter of the PPF. Due to these physical reasons, when the
desired critical dimension of a structure is near or below the alpha-parameter of the PPF, it may be just impossible to print the
structure because of the vanishing image contrast due to the blurring.
It was shown by means of the simulation feature of the ePLACE data prep package that in this situation a modification of both the
geometry and the dose assignment of the shapes will significantly increase the contrast of the deposited energy and thus, even preserve
the printability of critical structures. This geometrically induced dose correction (GIDC) method is implemented in the ePLACE
package. The simulation results for test structures are now validated by exposures of test patterns and its results clearly establish the
practical advantage of the new method.
In this paper we will publish the results of the related exposures - done on Vistec SB3050 series shaped e-beam writers -
demonstrating the practical importance of the GIDC method for layouts with critical dimensions of 32 nm and below.
KEYWORDS: Calibration, Monte Carlo methods, Photoresist processing, Electron beam lithography, Data modeling, Process modeling, Scanning electron microscopy, Computer simulations, Scattering, Chemically amplified resists
With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume
manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective
of the MAGIC high-throughput maskless lithography project [1] is the application of the physics-based simulation in a
virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction
methodologies [2]. To support this, a rigorous e-beam lithography simulator for the feature scale has been developed [3]. The
patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in
analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for
the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a
calibration process.
To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures
have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently
implemented model calibration methodology has been applied to determine the optimum set of resist model parameters.
While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for
verification.
In electron beam lithography, the electron scattering and the corresponding proximity effect highly influence the feature
resolution. Especially for sub-100 nm features a compensation for this effect is needed. There are several methods of
determination of the proximity parameters, which mostly are time-consuming and complex due to a need of an initial
proximity effect correction and immense measurement effort. In this paper the checkerboard pattern is proposed to
provide the opportunity for proximity parameter determination in a fast and easy manner without using a sophisticated
CD-SEM metrology. The concept is illustrated by simulation and first experimental results are shown.
KEYWORDS: Electron beam direct write lithography, Cadmium sulfide, Image processing, Printing, Line width roughness, Line edge roughness, Electron beams, Point spread functions, Photoresist processing, Metrology
For shortening the writing time, especially in shaped Electron Beam Direct Writing (EBDW), it is crucial to reduce
the number of shapes and the coverage of layout for exposure. The determination of conventional or reversed image
printing according to the process integration is one of the concerns for time and cost-effective process in the EBDW. We
have studied two different cases for the purpose above. First, the proximity effect correction (PEC) with dose
modification applied on each tone of resists, positive and negative, for the printing of conventional and reversed images.
The CDs that are obtained from the both printed images compared and are either with that from the simulations.
Secondly, the two different types of PEC, dose and shape modification, applied to a conventional image using an
identical point spread function (PSF). The line edge roughness (LER), line width roughness (LWR) and CDs in dose and
shape corrected conventional image pattern have been measured and compared. The MGS/PROXECCO was used for all
the preparation of exposure data mentioned above. In summary, we suggest the strategies of efficient PEC for the EBDW of contrasting images, propose the available method of PEC for the time-efficient EBDW, and for the further multiple EBDW developments.
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