Mr. Michael Bishop Profile

Michael Bishop

Associate Engineer at SUNY Poly SEMATECH

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Author

Publications (27)

Proceedings Article | 24 August 2010 Paper

Multipurpose instrument calibration standard for particle beam, scanned probe and optical microscopy: NIST reference material (RM) 8820

Michael Postek, András Vladar, William Keery, Michael Bishop, Benjamin Bunday, John Allgair

Proceedings Volume 7767, 77670D (2010) https://doi.org/10.1117/12.861595

KEYWORDS: Calibration, Scanning electron microscopy, Silicon, Contamination, Standards development, Scatterometry, Metrology, Lithography, Electron microscopes, Microscopes

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Proceedings Article | 3 June 2010 Paper

NEW scanning electron microscope magnification calibration reference material (RM) 8820

Michael Postek, András Vladár, William Keery, Michael Bishop, Benjamin Bunday, John Allgair

Proceedings Volume 7729, 77290D (2010) https://doi.org/10.1117/12.859118

KEYWORDS: Calibration, Scanning electron microscopy, Electron microscopes, Silicon, Contamination, Standards development, Lithography, Electroluminescent displays, Metrology, Scatterometry

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Proceedings Article | 2 April 2010 Paper

Reference material (RM) 8820: a versatile new NIST standard for nanometrology

Michael Postek, Andras Vladar, William Keery, Michael Bishop, Benjamin Bunday, John Allgair

Proceedings Volume 7638, 76381B (2010) https://doi.org/10.1117/12.848037

KEYWORDS: Calibration, Scanning electron microscopy, Silicon, Contamination, Standards development, Metrology, Lithography, Electron microscopes, Electroluminescent displays, Scatterometry

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Proceedings Article | 23 March 2009 Paper

Reference metrology in a research fab: the NIST clean calibrations thrust

Ronald Dixson, Joe Fu, Ndubuisi Orji, Thomas Renegar, Alan Zheng, Theodore Vorburger, Al Hilton, Marc Cangemi, Lei Chen, Mike Hernandez, Russell Hajdaj, Michael Bishop, Aaron Cordes

Proceedings Volume 7272, 727209 (2009) https://doi.org/10.1117/12.815499

KEYWORDS: Calibration, Metrology, Scanning electron microscopy, Standards development, Atomic force microscopy, Scanners, Nanotechnology, Profiling, Dimensional metrology, Semiconductors

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SPIE Journal Paper | 1 January 2008

Optical critical dimension measurement of silicon grating targets using back focal plane scatterfield microscopy

Heather Patrick, Ravikiran Attota, Bryan Barnes, Thomas Germer, Ronald Dixson, Michael Stocker, Richard Silver, Michael Bishop

JM3, Vol. 7, Issue 01, 013012, (January 2008) https://doi.org/10.1117/12.10.1117/1.2885275

KEYWORDS: Reflectivity, Diffraction, Silicon, Microscopy, Scanning electron microscopy, Optical testing, Objectives, Atomic force microscopy, Diffraction gratings, Microscopes

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Proceedings Article | 5 April 2007 Paper

TEM calibration methods for critical dimension standards

Ndubuisi Orji, Ronald Dixson, Domingo Garcia-Gutierrez, Benjamin Bunday, Michael Bishop, Michael Cresswell, Richard Allen, John Allgair

Proceedings Volume 6518, 651810 (2007) https://doi.org/10.1117/12.713368

KEYWORDS: Transmission electron microscopy, Calibration, Standards development, Crystals, Electron microscopes, Scanning electron microscopy, Metrology, Silicon, Atomic force microscope, Image resolution

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One of the key challenges in critical dimension (CD) metrology is finding suitable calibration standards. Over the last few years there has been some interest in using features measured with the transmission electron microscope (TEM) as primary standards for linewidth measurements. This is because some modes of TEM can produce lattice-resolved images having scale traceability to the SI (Systeme International d'Unites or International System of Units) definition of length through an atomic lattice constant. As interest in using calibration samples that are closer to the length scales being measured increases, so will the use of these TEM techniques. An area where lattice-traceable images produced by TEM has been used as a primary standard is in critical dimension atomic force microscope (CD-AFM) tip width calibration. Two modes of TEM that produce crystal lattice-traceable images are high resolution transmission electron microscope (HR-TEM) and high angle annular dark field scanning transmission electron microscope (HAADF-STEM). HR-TEM produces lattice-traceable images by interference patterns of the diffracted and transmitted beams rather than the actual atomic columns, while HAADF-STEM produces direct images of the crystal lattice. The difference in how both of these techniques work could cause subtle variations in the way feature edges are defined. In this paper, we present results from width samples measured using HR-TEM and HAADF-STEM. Next we compare the results with measurements taken from the same location by two different CD-AFMs. Both of the CD-AFM instruments used for this work have been calibrated using a single crystal critical dimension reference material (SCCDRM). These standards, developed by the National Institute of Standards and Technology (NIST) and SEMATECH, used HR-TEM for traceable tip-width calibration. Consequently, the present work and the previous SCCDRM work provide a mutual cross-check on the traceability of the width calibration. Excellent agreement was observed.

Proceedings Article | 24 March 2006 Paper

Optical critical dimension measurement and illumination analysis using the through-focus focus metric

Ravikiran Attota, Richard Silver, Michael Bishop, Ronald Dixson

Proceedings Volume 6152, 61520K (2006) https://doi.org/10.1117/12.656421

KEYWORDS: Microscopes, Cadmium, Critical dimension metrology, Silicon, Optical microscopes, Optical simulations, Scanning electron microscopy, Optical testing, Metrology, Calibration

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Proceedings Article | 24 March 2006 Paper

Litho-metrology challenges for the 45-nm technology node and beyond

John Allgair, Benjamin Bunday, Mike Bishop, Pete Lipscomb, Ndubuisi Orji

Proceedings Volume 6152, 61520C (2006) https://doi.org/10.1117/12.659059

KEYWORDS: Overlay metrology, Metrology, Critical dimension metrology, Scanning electron microscopy, Semiconducting wafers, Amorphous silicon, Reticles, Calibration, Manufacturing, Lithography

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Proceedings Article | 24 March 2006 Paper

Calibrating optical overlay measurements

W. Lipscomb, J. Allgair, B. Bunday, M. Bishop, R. Silver, R. Attota, M. Stocker

Proceedings Volume 6152, 615211 (2006) https://doi.org/10.1117/12.659597

KEYWORDS: Overlay metrology, Scanning electron microscopy, Atomic force microscopy, Calibration, Metrology, Interfaces, Semiconducting wafers, Line edge roughness, Optical testing, Wafer-level optics

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Proceedings Article | 24 March 2006 Paper

Scatterfield microscopy using back focal plane imaging with an engineered illumination field

Heather Patrick, Ravikiran Attota, Bryan Barnes, Thomas Germer, Michael Stocker, Richard Silver, Michael Bishop

Proceedings Volume 6152, 61520J (2006) https://doi.org/10.1117/12.656452

KEYWORDS: Reflectivity, Diffraction, Silicon, Scatterometry, Polarization, Diffraction gratings, Cameras, Illumination engineering, Data conversion, Microscopes

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Proceedings Article | 10 May 2005 Paper

High-resolution optical metrology

R. Silver, R. Attota, M. Stocker, M. Bishop, L. Howard, T. Germer, E. Marx, M. Davidson, R. Larrabee

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.606231

KEYWORDS: Overlay metrology, Metrology, Scatterometry, Critical dimension metrology, Illumination engineering, Scanning electron microscopy, Microscopy, Optical imaging, Scattering, Optical metrology

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Proceedings Article | 10 May 2005 Paper

Application of through-focus focus-metric analysis in high resolution optical metrology

Ravikiran Attota, Richard Silver, Thomas Germer, Michael Bishop, Robert Larrabee, Michael Stocker, Lowel Howard

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.621106

KEYWORDS: Fermium, Frequency modulation, Silicon, Indium arsenide, Destructive interference, Optical resolution, Optical metrology, Metrology, Process control, Optical microscopes

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Proceedings Article | 24 May 2004 Paper

High-resolution optical overlay metrology

Richard Silver, Ravikiran Attota, Michael Stocker, Michael Bishop, Jau-Shi Jun, Egon Marx, Mark Davidson, Robert Larrabee

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.539028

KEYWORDS: Overlay metrology, Metrology, Indium arsenide, Scanning electron microscopy, Lithographic illumination, Electromagnetism, Silicon, Data modeling, Optics manufacturing, Microscopes

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Proceedings Article | 24 May 2004 Paper

Determination of optimal parameters for CD-SEM measurement of line-edge roughness

Benjamin Bunday, Michael Bishop, Donald McCormack, John Villarrubia, Andras Vladar, Ronald Dixson, Theodore Vorburger, N. Orji, John Allgair

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535926

KEYWORDS: Line edge roughness, Line scan image sensors, Line width roughness, Edge roughness, Image segmentation, Critical dimension metrology, Metrology, Edge detection, Image quality, Tolerancing

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The measurement of line-edge roughness (LER) has recently become a topic of concern in the litho-metrology community and the semiconductor industry as a whole. The Advanced Metrology Advisory Group (AMAG), a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST), has a project to investigate LER metrics and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed, standardized solution for implementation. The 2003 International Technology Roadmap for Semiconductors (ITRS) has included a new definition for roughness. The ITRS envisions root mean square measurements of edge and width roughness. There are other possible metrics, some of which are surveyed here. The ITRS envisions the root mean square measurements restricted to roughness wavelengths falling within a specified process-relevant range and with measurement repeatability better than a specified tolerance. This study addresses the measurement choices required to meet those specifications. An expression for the length of line that must be measured and the spacing of measurement positions along that length is derived. Noise in the image is shown to produce roughness measurement errors that have both random and nonrandom (i.e., bias) components. Measurements are reported on both UV resist and polycrystalline silicon in special test patterns with roughness typical for those materials. These measurements indicate that the sensitivity of a roughness measurement to noise depends importantly both on the choice of edge detection algorithm and the quality of the focus. Measurements are less sensitive to noise when a model-based or sigmoidal fit algorithm is used and when the images are in good focus. Using the measured roughness characteristics for UV resist lines and applying the ITRS requirements for the 90 nm technology node, the derived expression for sampling length and sampling interval implies that a length at least 8 times the node (i.e., 720 nm) must be measured at intervals of 7.5 nm or less.

Proceedings Article | 24 May 2004 Paper

Dimensional metrology of resist lines using a SEM model-based library approach

John Villarrubia, Andras Vladar, Benjamin Bunday, Michael Bishop

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536871

KEYWORDS: Scanning electron microscopy, Electron beams, Model-based design, Silicon, Dimensional metrology, Statistical modeling, Metrology, Monte Carlo methods, Manufacturing, Semiconducting wafers

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Proceedings Article | 24 May 2004 Paper

Evaluation of new in-chip and arrayed line overlay target designs

Ravikiran Attota, Richard Silver, Michael Bishop, Egon Marx, Jau-Shi Jun, Michael Stocker, Mark Davidson, Robert Larrabee

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.539164

KEYWORDS: Overlay metrology, Fermium, Frequency modulation, Critical dimension metrology, Scanning electron microscopy, Diffraction gratings, Metrology, Process control, Cadmium, Silicon

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Proceedings Article | 24 May 2004 Paper

Results of benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node

Benjamin Bunday, Michael Bishop, John Allgair

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535960

KEYWORDS: Semiconducting wafers, Line edge roughness, Scanning electron microscopy, Pattern recognition, Contamination, Finite element methods, Standards development, Metrology, Lithography, Critical dimension metrology

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The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH Manufacturing Initiative (ISMI) consortium’s Member Companies and from the National Institute of Standards (NIST). The AMAG wrote and, in 2002, with CD-SEM supplier involvement, updated the “Unified Advanced CD-SEM Specification for Sub-130nm Technology (Version 2002)” to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2003 International Technology Roadmap for Semiconductors, and also conveys member companies’ other collective needs to vendors. Through applying this specification during the mid-2003 timeframe, a benchmarking effort of the currently available advanced CD-SEMs has been performed. These results are presented here. The AMAG Unified Specification includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter included in the benchmark, and, when applicable, prescribes a target specification compatible with the ITRS and methodologies compatible with the demands of 90nm technology. Parameters to be considered include: •Precision, Repeatability and Reproducibility •Accuracy, Apparent Beam Width and Resolution •Charging and Contamination •Tool-to-Tool Matching •Pattern Recognition and Navigation Accuracy •Throughput •Instrumentation Outputs •Tool Automation and Utility •Precision and Accuracy of Profile Measurement •Precision and Accuracy of Roughness Measurement. Previous studies under this same project have been published, with the initial version of the International Sematech Unified Specification in 1998, and multi-supplier benchmarks in 1999 and 2001. The results for the 2003 benchmark will be shown and compared to the ITRS, and composite viewpoints showing these 2003 benchmark results compared to the past results are also shown, demonstrating interesting CD-SEM industry trends.

Proceedings Article | 15 July 2003 Paper

Sidewall structure estimation from CD-SEM for lithographic process control

Philip Bingham, Jeffery Price, Kenneth Tobin, Thomas Karnowski, Marylyn Bennett, E. Hal Bogardus, Michael Bishop

Proceedings Volume 5041, (2003) https://doi.org/10.1117/12.485229

KEYWORDS: Scanning electron microscopy, Finite element methods, Feature extraction, Databases, Semiconducting wafers, Critical dimension metrology, Sensors, Lithography, Image retrieval, Electron beams

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Proceedings Article | 15 July 2003 Paper

CD-SEM measurement line-edge roughness test patterns for 193 nm lithography

Benjamin Bunday, Michael Bishop, John Villarrubia, Andras Vladar

Proceedings Volume 5041, (2003) https://doi.org/10.1117/12.485234

KEYWORDS: Line edge roughness, Reticles, Line width roughness, Scanning electron microscopy, Line scan image sensors, Edge roughness, Signal to noise ratio, Binary data, Lithography, Semiconductors

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Proceedings Article | 2 June 2003 Paper

Benchmarking of current generation overlay systems at the 130-nm technology node

Beth Russo, Michael Bishop

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.482674

KEYWORDS: Semiconducting wafers, Overlay metrology, Chemical mechanical planarization, Data modeling, Reticles, Metals, Silicon, Calibration, Copper, Curium

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Proceedings Article | 2 June 2003 Paper

CD-SEM measurement line-edge roughness test patterns for 193-nm lithography

Benjamin Bunday, Michael Bishop, John Villarrubia, Andras Vladar

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485007

KEYWORDS: Line edge roughness, Reticles, Line width roughness, Edge roughness, Line scan image sensors, Scanning electron microscopy, Signal to noise ratio, Binary data, Lithography, Metrology

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Proceedings Article | 2 June 2003 Paper

Specifications and methodologies for benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node and beyond

Benjamin Bunday, Michael Bishop

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483663

KEYWORDS: Semiconducting wafers, Scanning electron microscopy, Pattern recognition, Contamination, Line edge roughness, Electron beams, Critical dimension metrology, Metrology, Calibration, Semiconductors

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Proceedings Article | 2 June 2003 Paper

Quantitative profile-shape measurement study on a CD-SEM with application to etch-bias control and several different CMOS features

Benjamin Bunday, Michael Bishop, John Swyers, Kevin Lensing

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485016

KEYWORDS: Semiconducting wafers, Etching, Calibration, Critical dimension metrology, Deep ultraviolet, Process control, Scanning electron microscopy, Lithography, Photoresist processing, Reticles

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One goal of CD metrology is to monitor lithographic process control and how it relates to post-etch results. At present, in-fab process control for this purpose is achieved through top-down CD measurements. To acquire profile information requires destructive cross-section SEM measurements or time-consuming AFM measurements. To find height and profile information about a resist or etched structure directly on a CD-SEM, techniques using the combination of in-column beam tilt and stereographic imaging have been developed, implemented and improved on the Applied Materials NanoSEM-3D. This work is an extension of results previously published, although the tool used is greatly improved and the target feature stacks more thorough. The column of the NanoSEM-3D is designed to be able to electronically tilt the incident beam at small angles as it approaches the sample, through bending the beam within the column. Two images can be captured of the sidewall of the feature target, one at a smaller tilt angle and one at a larger tilt angle. Through matching common features between these two images, a reconstructed profile can be mathematically generated. A feature height and sidewall angle can be calculated, and general shape information such as top-rounding, footing and undercutting can also be displayed. To benchmark the effectiveness of this new technique, an experiment has been conducted to quantify the repeatability and reproducibility of height and sidewall angle measurements of lines of resist-on-poly and the resulting etched-poly lines, and correlate these to measurements of the these same profiles using XSEM to determine the accuracy of the technique. This study will span a reasonable lithographic process window. We hope to demonstrate the necessary precision and accuracy capability to non-destructively replace some cross-section work. In applying these techniques to a common etch bias problem, we also hope to demonstrate a strong correlation which can be used to directly predict post-etch behavior and serve as a model for other etch processes, work with which XSEM cross-sections have typically been used until now. The profile measurement technique is also applied to other CMOS features such as etched STI trench, resist and etched contact holes, and resist and etched damascene trenches and vias, with calculated tool precisions for feature height and sidewall angle.

Proceedings Article | 2 June 2003 Paper

Calibration strategies for overlay and registration metrology

Richard Silver, Michael Stocker, Ravikiran Attota, Michael Bishop, Jau-Shi Jun, Egon Marx, Mark Davidson, Robert Larrabee

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.488486

KEYWORDS: Calibration, Overlay metrology, Error analysis, Semiconducting wafers, Metrology, Detection and tracking algorithms, Standards development, Charge-coupled devices, Cameras, Statistical analysis

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Proceedings Article | 16 July 2002 Paper

Benchmarking of advanced CD-SEMs at the 130-nm CMOS technology node

Benjamin Bunday, Michael Bishop

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473444

KEYWORDS: Semiconducting wafers, Scanning electron microscopy, Contamination, Pattern recognition, Metrology, Electron beams, Aluminum, CMOS technology, Semiconductors, Lithography

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Proceedings Article | 16 July 2002 Paper

Overlay tool comparison for sub-130-nm technologies

Beth Russo, Michael Bishop, David Benoit, Richard Silver

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473464

KEYWORDS: Semiconducting wafers, Overlay metrology, Silicon, Chemical mechanical planarization, Data modeling, Time metrology, Metals, Wafer testing, Reticles, Calibration

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Proceedings Article | 16 July 2002 Paper

Quantitative profile-shape measurement study on a CD-SEM with application to etch-bias control

Benjamin Bunday, Michael Bishop, Marylyn Bennett, John Swyers, Zipora Haberman-Golan

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473452

KEYWORDS: Semiconducting wafers, Calibration, Etching, Critical dimension metrology, Scanning electron microscopy, Lithography, Line edge roughness, Cadmium, Error analysis, Process control

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Showing 5 of 27 publications

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