Mr. Michael Chemama Profile

Michael Chemama

at Applied Materials Israel, Ltd.

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Publications (1)

Proceedings Article | 26 May 2022 Presentation + Paper

Recess metrology challenges for 3D device architectures in advanced technology nodes

Gaetano Santoro, Kevin Houchens, Janusz Bogdanowicz, Moshe Elizov, Lior Yaron, Michael Chemama, Alex Goldenshtein, Amit Zakay, Noam Amit, Basoene Briggs, Antoine Pacco, Romain Delhougne, Andrew Cockburn, Yaniv Abramovitz, Aviram Tam, Ofer Adan, Hans Mertens, Anne-Laure Charley, Naoto Horiguchi, Philippe Leray, Gian Francesco Lorusso

Proceedings Volume 12053, 120530L (2022) https://doi.org/10.1117/12.2613771

KEYWORDS: Transmission electron microscopy, Metrology, Scanning electron microscopy, Metals, 3D metrology, Molybdenum, Tin, Semiconducting wafers, Signal to noise ratio, Process control

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ABSTRACT The introduction of new three-dimensional (3D) architectures in future logic and memory devices present new challenges for process metrology and control. Where there is a need to recess only one material type out of a superlattice (SL) layer stack, such structures all have in common the fact that the recess is hidden in the stack. Currently, process control in this field heavily relies on expensive, slow, and destructive metrology such as Transmission Electron Microscopy (TEM). In this work, we use the high voltage Scanning Electron Microscope (SEM) technique in combination with the Elluminator® improved Back-Scattered electrons (BSE) technology for better imaging efficiency to demonstrate the ability to measure cavity recess from top-down SEM images. We present case studies both in logic and memory domains. In Horizontal Gate-All-Around (H-GAA) Nanosheet and Forksheet logic devices, the SiGe layer is recessed in a Si/SiGe SL stack. In 3-Dimensional memory devices, we present results on Poly-Si recess metrology in Poly-Si/SiO₂SL stack, Molybdenum (Mo) recess metrology in a Mo/aSi SL stack, and TiN recess metrology in a 3DSCM stack used for memory word line. For the evaluation of the proposed recess metrology technique, several wafers with modulated recess amounts were measured using SEM technology at several high voltage landing energies (LE). BSE signal and advanced image analysis algorithms were used to build a prediction model and quantify the recessed amounts using an edge-based analysis. TEM metrology was used to validate the measurement based on the top-down high LE SEM images. We demonstrate that by using high voltage LE, in combination with enhanced BSE efficiency and advanced image analysis algorithms, we can investigate hidden layers in the stack, identify the recessed material edge, and measure accurately the cavities of interest, thus ultimately providing an inline, non-destructive, and statistically representative metrology solution for such advanced technology nodes. This new application will help chip manufacturers to characterize their processes faster and provide an HVM monitoring and control solution.

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