Ms. Morimi Osawa Profile

Morimi Osawa

at Fujitsu Ltd

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Publications (4)

Proceedings Article | 26 March 2013 Paper

Practical proof of CP element based design for 14nm node and beyond

Takashi Maruyama, Hiroshi Takita, Rimon Ikeno, Morimi Osawa, Yoshinori Kojima, Shinji Sugatani, Hiromi Hoshino, Toshio Hino, Masaru Ito, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada

Proceedings Volume 8680, 868027 (2013) https://doi.org/10.1117/12.2011678

KEYWORDS: Logic, Analog electronics, Semiconducting wafers, Mirrors, Metals, High volume manufacturing, Logic devices, System on a chip, Electron beam direct write lithography, Lithium

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To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count reduction is the essential key. All device circuits should be composed with predefined character parts and we call this methodology “CP element based design”. In our previous work, we presented following three concepts [2]. 1) Memory: We reported the prospects of affordability for the CP-stencil resource. 2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis. 3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated tracks and cutting points at the tile edges. In this paper, we will report the experimental proofs in these methodologies. In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1], we assumed total available CP stencil resource as 9000um². We should manage to layout all circuit macros within this restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput. In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance. For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design CP stencils to hit the target throughput within the area constraint. From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don’t need special CP design approach than legacy pattern matching CP extraction. From all these experimental results we get good prospects to the reality of full CP element based layout.

Proceedings Article | 4 March 2008 Paper

Global and local factors of on-chip variation of gate length

Morimi Osawa, Koji Hosono, Satoru Asai

Proceedings Volume 6925, 692508 (2008) https://doi.org/10.1117/12.772568

KEYWORDS: SRAF, Photomasks, Line width roughness, Critical dimension metrology, Electroluminescence, Cadmium, Lithography, Scanning electron microscopy, Transistors, Eye models

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Proceedings Article | 13 March 2006 Paper

Design-friendly DFM rule

Morimi Osawa, Takayoshi Minami, Hiroki Futatsuya, Satoru Asai

Proceedings Volume 6156, 61560G (2006) https://doi.org/10.1117/12.656271

KEYWORDS: SRAF, Design for manufacturing, Lithography, Optical proximity correction, Diffusion, Resolution enhancement technologies, Monte Carlo methods, Manufacturing, Data modeling, Bridges

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Proceedings Article | 28 May 2004 Paper

Model-based OPC/DRC considering local flare effects

Hiroki Futatsuya, Teruyoshi Yao, Morimi Osawa, Kozo Ogino, Hiromi Hoshino, Hiroshi Arimoto, Yasuhide Machida, Satoru Asai

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535076

KEYWORDS: Optical proximity correction, Printing, Photomasks, Model-based design, Semiconducting wafers, Light scattering, Diffraction, Acquisition tracking and pointing, Manufacturing, Lithography

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