Ms. Naya Ha Profile

Naya Ha

at SAMSUNG Electronics Co Ltd

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Author

Publications (6)

Proceedings Article | 29 March 2013 Paper

Model based hint for litho hotspot fixing beyond 20nm node

Jae-Hyun Kang, Byung-Moo Kim, Naya Ha, Hung bok Choi , Kee sup Kim , Sarah Mohamed, Kareem Madkour, Wael ElManhawy, Evan Lee, Jean-Marie Brunet, Joe Kwan

Proceedings Volume 8684, 86840N (2013) https://doi.org/10.1117/12.2011619

KEYWORDS: Lithography, Double patterning technology, Design for manufacturing, Resolution enhancement technologies, Manufacturing, Bridges, Visualization, Design for manufacturability, Metals, Electronics

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Proceedings Article | 15 March 2012 Paper

Thickness-aware LFD for the hotspot detection induced by topology

Jae-Hyun Kang, Naya Ha, Joo-Hyun Park, Byung-Moo Kim, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ahmed Mohy, Shady Abdelwahed, Mohamed Imam

Proceedings Volume 8327, 83270P (2012) https://doi.org/10.1117/12.917998

KEYWORDS: Semiconducting wafers, Metals, Process modeling, Image processing, Design for manufacturing, Chemical mechanical planarization, Optical proximity correction, 3D modeling, Photovoltaics, Scanning electron microscopy

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Proceedings Article | 15 March 2012 Paper

In-design process hotspot repair using pattern matching

Daehyun Jang, Naya Ha, Junsu Jeon, Jae-Hyun Kang, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ya-Chieh Lai, Philippe Hurat, Wilbur Luo

Proceedings Volume 8327, 83270S (2012) https://doi.org/10.1117/12.916199

KEYWORDS: Silicon, Manufacturing, Lithography, Failure analysis, Data processing, Chemical mechanical planarization, Semiconducting wafers, Design for manufacturability, Tolerancing, Optical lithography

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Proceedings Article | 15 March 2012 Open Access

Yield enhancement with DFM

Seung Weon Paek, Jae Hyun Kang, Naya Ha, Byung-Moo Kim, Dae-Hyun Jang, Junsu Jeon, DaeWook Kim, Kun Young Chung, Sung-eun Yu, Joo Hyun Park, SangMin Bae, DongSup Song, WooYoung Noh, YoungDuck Kim, HyunSeok Song, HungBok Choi, Kee Sup Kim, Kyu-Myung Choi, Woonhyuk Choi, JoongWon Jeon, JinWoo Lee, Ki-Su Kim, SeongHo Park, No-Young Chung, KangDuck Lee, YoungKi Hong, BongSeok Kim

Proceedings Volume 8327, 832704 (2012) https://doi.org/10.1117/12.920029

KEYWORDS: Design for manufacturing, Silicon, Polishing, Optical proximity correction, Back end of line, Metals, Failure analysis, Yield improvement, Logic, Manufacturing

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Proceedings Article | 5 April 2011 Paper

In-design DFM CMP flow for block level simulation using 32nm CMP model

Naya Ha, Jinwoo Lee, S. W. Paek, Kee Sup Kim, Kuang Han Chen, Aaron Gower-Hall, Tamba Gbondo-Tugbawa, Philippe Hurat

Proceedings Volume 7974, 79740W (2011) https://doi.org/10.1117/12.880899

KEYWORDS: Chemical mechanical planarization, Metals, Copper, System on a chip, Design for manufacturing, Manufacturing, Dielectrics, Polishing, Device simulation, Logic

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Proceedings Article | 13 March 2009 Paper

Enhanced layout optimization of sub-45nm standard: memory cells and its effects

Seung Weon Paek, Dae Hyun Jang, Joo Hyun Park, Naya Ha, Byung-Moo Kim, Hyo Sig Won, Kyu-Myung Choi, Kuang-Kuo Lin, Simon Klaver, Shobhit Malik, Michiel Oostindie, Frank Driessen

Proceedings Volume 7275, 72751M (2009) https://doi.org/10.1117/12.815413

KEYWORDS: Design for manufacturing, Semiconducting wafers, Yield improvement, Manufacturing, Laser induced breakdown spectroscopy, Standards development, Tolerancing, Optimization (mathematics), Optical proximity correction, Silicon

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Showing 5 of 6 publications

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