EUV lithography has already introduced in high volume manufacturing and continuous improvements has allowed to resolve pitch 24nm line and space (L/S), pitch 32nm contact hole and pillar pattern with single exposure at even numerical aperture (NA) 0.33. However, pattern roughness, local critical dimension uniformity (LCDU) and process related defects are still major challenges with decreasing critical dimensions (CD). Pitch downscaling also require the use of thinner photoresist mask to prevent pattern collapse from high aspect ratios. Thinner photoresist mask is challenging for pattern transfer because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. It is required to investigate a co-optimization of lithography processes, underlayers and etch processes to further EUV patterning extension. In this paper, our latest developed process solutions to extend the limits of EUV patterning will be reported. The advanced performance for metal oxide resists (MOR) will be introduced, with a focus on defect mitigation, dose reduction strategies and CD stability.
As the semiconductor industry progresses towards the 2nm logic technology node in pursuit of improved chip performance and density, the demand for minimum pitch scaling in the back-end-of-line (BEOL) interconnect becomes crucial. Imec N3 logic design rules defined a minimum Metal 2 (M2) layer pitch of 30 nm, representing 2nm technology nodes. To further enhance semiconductor integrated circuit performance, attention is shifting towards advanced mask materials for current 0.33 NA EUV scanners. Low-n masks have been shown to improve extreme ultraviolet (EUV) imaging performance in terms of Local-CDU (LCDU), reduced mask 3D effects and improved optical contrast compared to a Tabased mask. In our study, we observed notable enhancements in optical contrast for real logic designs using a low-n mask. Our findings demonstrate an impressive LCDU of 5.5 nm and CGDU of 5.5 nm for Place’n’Route (PnR) structures at a pitch of 32. Furthermore, we successfully printed tip-to-tip (T2T) features as small as 20 nm on the wafer for regular tip-to-tip structures that didn’t get any Optical proximity Correction (OPC). These advancements mark significant progress towards manufacturability and developing a holistic patterning approach for random logic metal with EUV.
Extreme ultraviolet (EUV) lithography has already introduced in high volume manufacturing and continuous improvements has allowed to resolve pitch 24 nm line and space (L/S), pitch 32 nm contact hole and pillar pattern with single exposure at even numerical aperture (NA) 0.33. However, pattern roughness, local critical dimension uniformity (LCDU) and process related defects are still major challenges with decreasing critical dimensions (CD). Pitch downscaling also require the use of thinner photoresist mask to prevent pattern collapse from high aspect ratios. Thinner photoresist mask is challenging for pattern transfer because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. It is required to investigate a co-optimization of lithography processes, underlayers and etch processes to further EUV patterning extension. In this paper our latest developed technology and process solutions to extend the limits of EUV patterning will be report.
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