In today’s advanced semiconductor process manufacturing, critical dimensions of device features have decreased to a few nanometers while the aspect ratios have increased beyond 100. The cost of process development has significantly increased and the performance of the lithography and plasma etch patterning processes are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a three-dimensional Monte Carlo-based feature scale model, ProETCH®, has been developed for modeling etch process with the capability of optimizing the process by solving forward and inverse problems. The shallow trench isolation etch process in self-aligned double patterning was investigated. The mechanism of silicon etch by Ar/Cl2 plasma was developed with experimental data as a reference. The developed model captures the trends and has quantitative accuracy in comparison to the experimental data, and can be used to identify the different fundamental pathways which contribute to the profile metrics. The developed model was then used to solve the forward problem, which is to predict profiles at different process conditions, and the inverse problem, which is to search for the process conditions (e.g, power and pressure) which could result in desirable profiles.
KEYWORDS: Etching, System on a chip, Plasma, Lithography, Semiconducting wafers, Photoresist materials, 3D modeling, Back end of line, Numerical simulations
A double patterning Litho-Etch-Litho-Etch (LELE) process developed in a test vehicle for Back End of Line manufacturing is investigated using rigorous, physics-based three-dimensional computational models. The wafer topography consists of TiN, SiO2, Spin-on-Carbon, Spin-on-Glass (SOG), over which the photoresist patterns are printed. The lithography step of the LELE flow is simulated using PROLITH, and the etching steps are simulated using ProETCH, a new dry etch simulator developed at KLA. Two clips that are spatially close to another and present in the photomask layout for the first and second lithography steps are considered to investigate the impact of etch process conditions on etch bias. We found that the final etch bias during the LELE processes is dominantly induced during the etch of SOG. The tapered profiles induced during the SOG etch process are due to the polymerization by CFx radicals produced in the plasma. The effect of varying the neutral-ion-flux ratio on the etch bias is investigated. Etch process development for SOG needs to balance multiple targets to avoid defect formation.
Conference Committee Involvement (3)
Advanced Etch Technology and Process Integration for Nanopatterning XIV
23 February 2025 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XIII
26 February 2024 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XII
28 February 2023 | San Jose, California, United States
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