Extreme ultraviolet lithography (EUVL) systems struggle from both low source brightness and low source throughput through the tool. For these reasons, photon shot noise will play a much larger role in image process development for EUVL than in DUV processes. Furthermore, the lower photon count increases the stochastic variation of all the processes which occur after photon absorption. This causes the printed edge to move away from the mean edge with some probability. This paper will present a model form and calibration flow for including stochastic probability bands in compact models suitable for full chip simulation. This model form relies on calibrating to statistical data from a rigorous EUV stochastic lithography model calibrated to wafer experimental data. The data generation, data preparation, and model calibration flows for the compact stochastic probability bands will be presented. We will show that this model form can predict patterns which are prone to stochastic pattern failure in realistic mask designs, as well as how this model form can be used downstream for full chip correction (e.g., SMO, OPC and/or ILT).
Multilayer unit thickness variations in the multilayer extreme ultraviolet (EUV) reflector stack pose a difficult problem for generation of lithographic models for use in Optical Proximity Correction (OPC). The multilayer stack is ideally comprised of alternating layers of molybdenum and silicon. However, there are diffused interface regions between these layers that might have slight variations in thickness, reflectance, and absorption. These interface regions can differ within specified parameters based on variations in the deposition tool, resulting in EUV masks with minor differences in the multilayer. This is a difficult problem for OPC models, because slight variations in the multilayer can result in large variations in the feature printed on the wafer. Also, these stack variations are not precisely known for every reticle, rather a sample stack is used to gather data from a cross section of a representative reticle.
This study explores the relationship between EUV mask stack reflectivity and horizontal to vertical pattern bias. In this computational study, the MoSi2 thickness is varied at systematic locations in the mask stack, then data on horizontal to vertical bias (H to V bias) for multiple features are gathered. The data will be used to understand the relationship between mask substrate reflectance, mask material thickness, and H to V bias. The study will also investigate the impact of high numerical aperture (0.55 NA anamorphic) imaging on the final H to V bias. Initial work indicates that a 1% variation in substrate reflectance results in approximately a 4% variation in CD.
Extreme ultraviolet (EUV) lithography at 13.5 nm stands at the crossroads of next generation patterning technology for high volume manufacturing of integrated circuits. Photo resist models that form the part of overall pattern transform model for lithography play a vital role in supporting this effort. The physics and chemistry of these resists must be understood to enable the construction of accurate models for EUV Optical Proximity Correction (OPC). In this study, we explore the possibility of improving EUV photo-resist models by directly correlating the parameters obtained from experimentally measured atomic scale physical properties; namely, the effect of interaction of EUV photons with photo acid generators in standard chemically amplified EUV photoresist, and associated electron energy loss events. Atomic scale physical properties will be inferred from the measurements carried out in Electron Resist Interaction Chamber (ERIC). This study will use measured physical parameters to establish a relationship with lithographically important properties, such as line edge roughness and CD variation. The data gathered from these measurements is used to construct OPC models of the resist.
As the critical dimension keeps shrinking, mask topography effect (Mask3D) becomes considerable to impact the lithography modeling accuracy and the quality of full-chip OPC. Among many challenges in Mask3D modeling, it is critical and particularly demanding to treat off-axis illumination (OAI) properly. In this paper, we present a novel Mask3D model that is completely test pattern- and optics- independent. Such model property enables greatly improved performance in terms of accuracy and consistency on various pattern types (1D/2D) and through a wide range of focus conditions, while no runtime overhead is incurred. The novel model and formulation will be able to save significant modeling time and greatly improve the model reliability, predictability and ease of use. Experimental results validate the claims and demonstrate the superiority to the current state-of-the-art Mask3D modeling method. This is a new generation Mask3D modeling process.
Mask topography (Mask3D) effect is one of the most influential factors in sub-28 nm technology node. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. In the meanwhile, Mask3D modeling must be able to handle the off-axis illumination (OAI) condition accurately. In this paper, we propose our full chip Mask3D modeling method which is an extension to the edge-based Mask3D model. In our modeling flow, we first review the edge-based Mask3D model and then analyze the impact from the off-axis source. We propose a parameter-based extension to characterize the off-axis impact efficiently. We further introduce two methods to calibrate the OAI-aware parameters by using rigorous or wafer data as the reference. Our experimental results show the great calibration accuracy throughout the defocus range with OAI sources, and validate the accuracy of our two parameter calibration approach.
As the technology node keeps shrinking down to sub-28 nm, mask topography (Mask3D) effect is one of the most influential factors to draw intensive research lately. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. Different approaches have been tried to resolve the difficulties in the full-chip modeling, but so far none of the existing Mask3D modeling methods have succeeded in meeting all the three criterion at the same time. It is often seen that an existing Mask3D model to succeed in one or two criteria, but fails in the rest. In this paper, we propose our innovative full chip Mask3D modeling method to successfully handle the above criterion at the same time. To our best of knowledge, it is the first ever Mask3D modeling in literature that is be able to achieve this goal. In our modeling flow, we first analyze the Mask3D effect by using rigorous simulation as the reference and generate edge-based kernels to mimic the Mask3D effect near the feature boundaries. The flexibility of handling the kernel helps us enable the support for all-angle patterns and be extendable for edge coupling effect and off-axis illumination. Our experimental results show that with only less than 30% runtime overhead compared to the conventional Mask2D model, we are able to achieve less than 0.8 nm CD RMS on the flexible feature patterns. An ILT-based OPC and simulation result is provided to validate the capability of all-angle support of our proposed model.
As modern photolithography feature sizes reduce, the use of sub-resolution assist features (SRAFs) to improve the
manufacturing process window has become more prevalent. Beyond the assist features placement based on rules, a
model based assist feature (MBAF) flow is needed to optimize the shape and the size of SRAFs, so that the process
margin of the main features (MFs) is maximized. In the MBAF flow, a vital component is to build an accurate model
that specifically checks the printability of SRAFs, which are supposed to leave no trace on wafer. Compared to the
traditional optical proximity correction (OPC) model, the SRAF printability check model faces extra challenges, for
example, the small size of SRAFs makes their direct transfer to the mask pattern more difficult, the SRAFs are usually
not measurable on wafer and the worst-case SRAFs printability is typically at off-nominal conditions. In this paper, we
propose an innovative binary modeling method for SRAF printability check model, which does not require the
measurement of SRAFs' size on wafer and yet provides accurate prediction of SRAFs printing on wafer. In this
modeling method, the binary determination of whether an SRAF prints/does not print (i.e., clean) on wafer was acquired
by inspecting the SEMs taken from real wafer measurements. Then the local extrema of the signal intensity around the
SRAFs was simulated and used to classify print/clean groups of SRAFs, and a special cost function was designed to
separate the print SRAFs and clean SRAFs as much as possible during model calibration.
As the semiconductor industry moves to the 45nm node and beyond, the tolerable
lithography process window significantly shrinks due to the combined use of high NA
and low k1 factor. This is exacerbated by the fact that the usable depth of focus at 45nm
node for critical layer is 200nm or less. Traditional Optical Proximity Correction (OPC)
only computes the optimal pattern layout to optimize its patterning at nominal process
condition (nominal defocus and nominal exposure dose) according to an OPC model
calibrated at this nominal condition, and this may put the post-OPC layout at nonnegligible
patterning risk due to the inevitable process variation (defocus and dose
variations). With a little sacrifice at the nominal condition, process variation aware OPC
can greatly enhance the robustness of post-OPC layout patterning in the presence of
defocus and dose variation. There is also an increasing demand for through process
window lithography verification for post-OPC circuit layout. The corner stone for
successful process variation aware OPC and lithography verification is an accurately
calibrated continuous process window model which is a continuous function of defocus
and dose. This calibrated model needs to be able to interpolate and extrapolate in the
usable process window. Based on Synopsys' OPC modeling software package ProGen,
we developed and implemented a novel methodology for continuous process window
(PW) model, which has two continuous adjustable process parameters: defocus and dose.
The calibration of this continuous PW model was performed in a single calibration
process using silicon measurement at nominal condition and off-focus-off-dose
conditions which are sparsely sampled within the measured entire focus exposure matrix
(FEM). The silicon data at the off-focus-off-dose conditions not used for model
calibration was utilized to validate the accuracy and stability of PW model during model
interpolation and extrapolation. We demonstrated this novel continuous PW modeling
approach can achieve very good performance both at nominal condition and at
interpolated or extrapolated off-focus-off-dose conditions.
In modern photolithography as the feature sizes reduce, the simulation of manufacturing process calls on more and
more accurate grasp of various effects in the process. While the optical simulation is calculated precisely by both firstprinciple
simulators and optical proximity correction (OPC) model simulator, an accurate and computational inexpensive
resist model has yet to be developed. After the exposure, resist parameters change the resist part of the proximity
effects by either moving the "optical image" or responding differently to varying image qualities. By inspecting the
wafer data, one can only see the results after development, which is the mixture of optical and resist effects. To isolate
the effect contributed by resist, it is necessary to separate the optical component and resist component. In this paper, a
novel method is proposed to determine the resist bias from the iso-focal structure, the critical dimension (CD) of which
was measured under different defocus conditions. The results extracted from experiments indicate that a constant CD
bias can catch most of resist effect at the first order of approximation.
Topographic mask effects can no longer be ignored at technology nodes of 45 nm, 32 nm and beyond. As
feature sizes become comparable to the mask topographic dimensions and the exposure wavelength, the popular
thin mask model breaks down, because the mask transmission no longer follows the layout. A reliable mask
transmission function has to be derived from Maxwell equations. Unfortunately, rigorous solutions of Maxwell
equations are only manageable for limited field sizes, but impractical for full-chip optical proximity corrections
(OPC) due to the prohibitive runtime. Approximation algorithms are in demand to achieve a balance between
acceptable computation time and tolerable errors.
In this paper, a fast algorithm is proposed and demonstrated to model topographic mask effects for OPC
applications. The ProGen Topographic Mask (POTOMAC) model synthesizes the mask transmission functions
out of small-sized Maxwell solutions from a finite-difference-in-time-domain (FDTD) engine, an industry leading
rigorous simulator of topographic mask effect from SOLID-E. The integral framework presents a seamless solution
to the end user. Preliminary results indicate the overhead introduced by POTOMAC is contained within the same order of magnitude in comparison to the thin mask approach.
In the modern photolithography simulation, the computation demand on resolution enhancement techniques (RETs) and optical proximity corrections (OPCs) is proportional to the simulation runtime of the model, which is dependant on the number of the kernels retained with the constrain of the model accuracy. Thus, it is essential to retain as few kernels as possible in the model calibration. Traditionally, the kernels are retained based upon their contribution to the aerial image, which is solely determined by the magnitudes of the eigenvalues. This method works well for arbitrary photolithography masks. However, real masks are never arbitrary and random. Instead, they have regular shapes and arrangements as governed by design rules, indicating the contributions from the retained kernels are statistically correlated to each other. By taking such correlations into account, the system representation can be improved to contain fewer Kernels for constant model accuracy. In this paper, the mathematical derivation of the pattern correlation concept is discussed and the concept is applied to a poly-silicon layer illuminated by a Quasar optical system with λ = 193 nm and NA = 0.8. Significant improvement of model kernel representation is observed, 12 improved kernels vs 20 original kernels, and the new methodology is justified by comparing the difference of the aerial image intensities between the full kernel representation and the retained kernels representation at sampling points.
In modern photolithography, the dose latitude, Normalized Image Log Slope (NILS), and hence the image quality
are closely related to the gradient of the aerial image intensity at the evaluation point. The placement of sub-resolution
assist feature (SRAF) in isolated lines helps improve the aerial image quality by increasing the gradient. Traditionally, it
is simple and straightforward to calculate the effect of the SRAF placement on the gradient at a certain evaluation point.
The gradients before and after the SRAF placement are computed separately. The difference between these two gradients
indicates the magnitude of the effect. However, this simple methodology is only convenient when the location of the
SRAF placement is known. In addition, this methodology is not adaptable to searching for the optimum placement, as
many potential placements need to be evaluated. In this report, an innovative and rapid solution for SRAF placement is
presented. The methodology output indicates the optimal location for the SRAF placement to increase the gradient of the
aerial image is about 210 nm from the drawn edge of the iso-line and is independent of the iso-line structure for an
annular illumination system. The results are verified by measuring the gradient difference with an independent tool.
Liberal use of assist features of both tones is an important component of the 45nm lithography strategy for many
layers. These features are often sized at λ/4 on the mask or smaller. Under these conditions, formerly successful
approximations of the mask near field using boundary layer methods or domain decomposition methods break
down. Rigorous simulations of the mask near field must include a three-dimensional (3D) Maxwell's equation
analysis, but these computations are cost-prohibitive for full-chip OPC, RET, and lithographic compliance
checking applications.
The purpose of this paper is to describe a simple and computationally efficient method that can improve model
fidelity for 45nm assist features of either tone, while still retaining computational simplicity. While the model
lacks the generality of a rigorous solution of Maxwell' sequations, it can be well-anchored to the real physics by
calibrating its performance to a lithographic TCAD mask simulator. The approach provides a balanced tradeo.
between speed and accuracy that makes it a superior approach to boundary layer and domain decomposition
methods, while retaining the capability to realistically be deployed on a full-chip lithography simulation.
Good OPC model calibration structures should be representative of and span the dimensions and layout forms that will be found in the product on which the model will be applied. If model fitting is done using edge placement (EPE) methods, only symmetric structures can be used and this constrains the model fitter to a classic but limited set of calibration structures. The most critical features, such as those from a bit cell tend to be asymmetric. While asymmetric structures have typically been used for model verification, using them in model calibration structures provides more degrees of freedom for the calibration test structures to capture two dimensional behavior. This produces more robust, accurate models which yield better quality corrections on wafer. During process development models are re-calibrated as the process is adjusted and optimized. In some cases particularly important critical configurations can be added to the calibration set to insure maximum accuracy on those features. As these configurations are extracted from real designs, they are rarely symmetric. This paper describes how by using a CD-based rather than an edge-placement based modeling approach, OPC models can be created from asymmetric, more product-like type structures, and demonstrates how this can allow better predictability on other verification structures. The paper will also review the two types of model forms commonly used (Constant and Variable Threshold models) and compare their performance while using asymmetric calibration structures.
An accurate process model is the linchpin of model-based Optical Proximity Correction (OPC) and Resolution Enhancement Technique (RET) synthesis. The accuracy of the resulting mask layout can be no better than that of the model. Relatively good, first-principle mathematical models exist for some process steps, such as aerial image formation, but resulting silicon is a combination of many effects, including those less well understood. Accuracy can be assured only with models anchored to observed phenomena. Process models are usually a combination of first principle elements and phenomenological components with the “right” degrees to freedom to fit the overall process. The key challenge in generating accurate models is to capture all process behavior over all conditions with a minimum number of empirical measurements. This means that models must extrapolate accurately from the specifics measured, and should be largely immune to empirical measurement noise. In this paper we describe a methodology in which to test model performance with respect to these criteria.
As an important resolution enhancement technique (RET), alternating aperture phase shift masks (AAPSM) has been widely adopted in 90 nm technology node and beyond. Mask topographical effect due to the 3D nature of the shifter features is becoming an increasingly important factor in lithography modeling. Rigorous 3D modeling of PSM is very computationally demanding thus impractical for full chip optical proximity correction (OPC). Here we introduce an alternative approach employing boundary layers to effectively approximate the 3D mask effect. We will present the model calibration versus real wafer data using the boundary layers and the corresponding OPC correction flow.
Model-based optical proximity correction (OPC) calculates pattern adjustments by simulating the layout with calibrated lithography and process models. OPC can only correct systematic lithography deviations, those error components that repeat chip to chip. OPC cannot compensate random deviation error components from unpredictable process variations, such as defocus and dose. However the ranges of variation from random effects is predictable, and OPC can optimize correction shapes to minimize this range where possible. Current techniques for supporting this optimization involve applying a set of models covering the range of expected process variations in defocus and exposure. Variation is assessed by comparing process corner-point model evaluations. Because there is a significant runtime cost simulating multiple process conditions, most production OPC jobs use a single, representative model (typically the "nominal" process condition) aided with rules and other heuristics to help handle process window effects.
In this paper the application of a new type of model that can be used to predict process variation with a single simulation call. The model involved in these studies targets pattern behavior as the focus offset deviates from the nominal focus setting. Used in conjunction with a nominal process model, this model can support process-window optimized OPC without the need for multiple models at various defocus settings. This model can also be used by itself to assess the defocus robustness of any configuration before or after OPC, thereby supporting efficient model-based layout verification.
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