Semiconductor processing has been advancing from the nano to the atomic scale. For atomic-scale processing, the plasma source need to be precisely controlled to minimize damage, such as UV radiation damage, ion-induced damage, and charge accumulation damage. In this presentation, we will introduce an Ultra Low Electron Temperature (ULET) plasma (Te < 0.5 eV) as a novel plasma source enabling us to perform damage-free plasma processing. We will also explain how to produce the ULET plasma. It is demonstrated that charge accumulation even in a patten with high aspect ratio is almost eliminated, and graphene remains undamaged in the ULET plasma, while it is heavily damaged in conventional plasma processes. The ULET plasma shows great promise for applications in atomic-scale plasma processing.
Continuous scaling by extreme ultraviolet (EUV) lithography is tightening the patterning requirements for photoresist materials. Specifically, chemically amplified resists (CAR) are facing significant challenges to keep supporting the patterning needs. In view of this, complementing EUV lithography with directed self-assembly (DSA) of block copolymers offers interesting opportunities to enable the use of CAR towards ultimate resolution. As DSA decouples the resist patterning performance from the final pattern quality, roughness and defects in the resist pattern can be rectified. Here, we discuss the impact of material and process parameters on the rectification performance by DSA, both for line-space and hexagonal contact hole arrays.
To further enable device scaling in HVM, new patterning materials are needed to meet the more stringent requirements such as line width and edge roughness (LWR and LER), dose sensitivity, pattern collapse, etch resistance and defectivity. The continuous progression of the shrinking of resist feature sizes will be accompanied by the scaling-down of the resist film thickness to prevent pattern collapse and to compensate for low depth-of-focus for high-NA EUV lithography. However, if we reduce the resist film thickness, we must also reduce the underlayer (UL) hardmask film thickness for optimum pattern transfer. As an alternative to spin-on underlayers, deposited ULs can be a potential candidate as it is possible to produce very thin uniformly deposited ULs, with the freedom to incorporate different elements to improve adhesion and modify etch selectivity. In this paper, we will discuss deposited ULs with film thickness scaled down to 3.5 nm for EUV lithography patterning as well as etch performance for pitch 32 and 28 line/space structures. We will also discuss about the possibility to modify the ULs to match the surface energy of the photoresist in use in order to minimize pattern collapse. Additionally, with scaled-down deposited ULs, we were able to obtain very similar post-litho unbiased roughness values (LWR 2.23 nm and LER 1.7 nm) as 10 nm spin-on reference UL (LWR: 2.26 nm and LER 1.66 nm). We will discuss more such details in terms of surface roughness, dose sensitivity, post-litho and post-etch LWR, LER, pattern collapse and defectivity in the presentation. Such ULs could become useful for high-NA EUV lithography when the litho stack is expected to scale down in thickness.
Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.
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