Mr. Ray Hsu Profile

Ray Hsu

Technical Sales Manager at Dow Chemical Co

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Publications (7)

Proceedings Article | 20 March 2015 Paper

Top-coatless 193nm positive-tone development immersion resist for logic application

Lian Cong Liu, Tsung Ju Yeh, Yeh-Sheng Lin, Yu Chin Huang, Chien Wen Kuo, Wen Liang Huang, Chia Hung Lin, Chun Chi Yu, Ray Hsu, I-Yuan Wan, Jeff Lin, Kwang-Hwyi Im, Hae Jin Lim, Hyun Jeon, Yasuhiro Suzuki, Cheng Bai Xu

Proceedings Volume 9425, 94251T (2015) https://doi.org/10.1117/12.2086348

KEYWORDS: Polymers, Lithography, Photoresist processing, Diffusion, Logic, Photoresist materials, 193nm lithography, Photoresist developing, Photomasks, Polymerization

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Proceedings Article | 13 March 2012 Paper

Studies of the source and mask optimization for 20nm node in the active layer

Chih-I Wei, Ruei-Hung Hsu, Yung-Feng Cheng, Ming-Jui Chen

Proceedings Volume 8326, 83262J (2012) https://doi.org/10.1117/12.917994

KEYWORDS: Source mask optimization, Photomasks, Semiconducting wafers, 3D modeling, Resolution enhancement technologies, Lithography, Scanning electron microscopy, Optical proximity correction, Molybdenum, Wafer-level optics

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Proceedings Article | 15 April 2008 Paper

Reflection control for immersion lithography at 45/32-nm nodes

Wan-Ju Tseng, Ruei-Hung Hsu, Shu Huei Hou, Tzu-Huai Tseng, Bill Lin, Chun Chi Yu, Sue Ryeon Kim, Jeong Yun Yu, Gerald Wayton, Maurizio Ciambra, Suzanne Coley, David Praseuth, Nick Pugliano

Proceedings Volume 6923, 69232Z (2008) https://doi.org/10.1117/12.776671

KEYWORDS: Metals, Lithography, Reflectivity, Optical lithography, Line width roughness, Immersion lithography, Reflection, Logic devices, Critical dimension metrology, Etching

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Proceedings Article | 5 April 2007 Paper

Use of in-line AFM as LWR verification tool in 45nm process development

Ming Hsun Hsieh, Kun Ho Shi, J. H. Yeh, Ruei Hung Hsu, Mingsheng Tsai, S. F. Tzou

Proceedings Volume 6518, 651833 (2007) https://doi.org/10.1117/12.712537

KEYWORDS: Critical dimension metrology, Line width roughness, Transmission electron microscopy, Optical proximity correction, Atomic force microscopy, Error analysis, Nondestructive evaluation, Semiconductors, Line edge roughness, Scanning electron microscopy

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Proceedings Article | 24 March 2006 Paper

65-nm photolithography process window qualification study with advanced e-beam metrology and inspection systems

Ruei Hung Hsu, Benjamin Szu-Min Lin, Wei-Yih Wu, Hong Xiao, Jack Jau

Proceedings Volume 6152, 61524K (2006) https://doi.org/10.1117/12.657356

KEYWORDS: Semiconducting wafers, Inspection, Photomasks, Finite element methods, Defect inspection, Critical dimension metrology, Scanning electron microscopy, Optical lithography, Etching, Photoresist materials

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Proceedings Article | 4 May 2005 Paper

Global planarization of gap-filling process for low-k dual damascene applications

Ruei Hung Hsu, I. Huang, Ling Chieh Lin, Benjamin Szu-Min Lin

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.600408

KEYWORDS: Coating, Etching, Semiconducting wafers, Lithography, Photoresist materials, Optics manufacturing, Optical lithography, Copper, Scanning electron microscopy, Critical dimension metrology

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Proceedings Article | 14 May 2004 Paper

Optimization of resist shrink techniques for contact hole and metal trench ArF lithography at the 90-nm technology node

Christine Wallace, Jochen Schacht, I Huang, Ruei Hsu

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.534610

KEYWORDS: Photoresist processing, Critical dimension metrology, Glasses, Lithography, Semiconducting wafers, Etching, Line edge roughness, Scanning electron microscopy, Metals, Reticles

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Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrink and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists’ glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.

Showing 5 of 7 publications

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