In the initial stage of advanced packaging, it was applied to CSWLP (Chip-Scale-Wafer-Level-Package) mainly for the package form-factor reduction. However, advanced packaging is used not only for the package size reduction but also for many remarkable features including Fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth. Advanced packaging will also play a key role in the upcoming heterogeneous integration. Canon developed the first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. Furthermore, we will report our low distortion patterning solution of our latest packaging stepper, FPA-5520iV LF2 option.
Advanced packaging was applied during the early stages of CSWLP (Chip-Scale-Wafer-Level-Package) development for mainly package form-factor reduction. However, advanced packaging is used not only for package size reduction but also for many remarkable features including fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth computing power. Advanced packaging will also play a key role in the upcoming Chiplet era. Canon developed our first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. In addition, we study bonding error budgets for fine pitch bump package in the upcoming Chiplet era. We will compare bonding errors among Silicon interposers, Organic interposers, and Glass interposers and point out the importance of lithography tool distortion reduction to realize less than 10 µm bump pitch packages. Furthermore, we will report on our low distortion patterning solution, the FPA-5520iV LF2 advanced packaging stepper.
KEYWORDS: Semiconducting wafers, Overlay metrology, Inspection, Signal processing, Optical alignment, Distortion, Signal detection, Film thickness, Metrology, Signal intensity
With the increasing complexity of semiconductor manufacturing processes and high overlay accuracy requirements, it is increasingly necessary to measure wafer characteristics accurately. When wafer distortion in shape and mark quality changes occur due to wafer characteristic changes, the measurement accuracy in overlay and wafer alignment decreases, resulting in lower yields. Canon has released the stand-alone wafer metrology tool (MS-001) as a solution for high accuracy wafer measurement. It has been reported that high productivity and overlay accuracy can be achieved by measuring the wafer distortion and exposing the wafer aligned based on the measurement results in the exposure system. In this report, the feasibility of detecting the mark quality changes, which is one of the factors of low measurement accuracy, was verified using product wafers. Moreover, it was demonstrated that MS-001 was successful in detecting wafer process variations with high accuracy. These results indicate that MS-001 can solve the issues caused by complex semiconductor manufacturing processes.
As wafer process complexity increases, demand for precise overlay accuracy including measurement of wafer deformation in advanced photolithography processes has increased. In general, wafer deformation can be measured with high accuracy by obtaining wafer alignment position information at multiple sites on a wafer. However, when a photolithography exposure system is used to perform the necessary wafer alignment measurements to improve overlay accuracy, the productivity of the exposure system will be drastically reduced due to the increase in total alignment measurement time. Canon developed the stand-alone wafer metrology tool (MS-001) as a solution to improve the overlay accuracy and the productivity of semiconductor manufacturing. MS-001 is used to perform Feed Forward Alignment (FFA) correction in which the wafer deformation is measured before the wafer is transferred to the exposure system and the data is sent to the exposure system. This reduces the number of alignment measurements required in the exposure system, making it possible to combine high productivity with high overlay accuracy. MS-001 also features improved selectivity of measurement marks by image detection and enhanced selectivity of measurement wavelengths by a new alignment light source unit (Hi-ALS). These allow MS-001 to select the optimal measurement mark and wavelength according to the wafer process. In addition, it has become possible to monitor process changes as well as alignment. In this paper, we demonstrated the performance of MS-001 and overlay accuracy improvement by FFA correction using DRAM product wafers. And we also verified the feasibility of a wafer monitor function using MS-001 to detect wafer deformation occurring in the manufacturing process. These results show that MS-001 can solve the challenges posed by complex processes. These results indicate that MS-001 has the potential to solve challenges caused by complex processes.
KEYWORDS: Data modeling, Semiconducting wafers, Overlay metrology, Machine learning, 3D modeling, Lithography, Data acquisition, Wafer testing, Target detection, Process modeling
As a part of the semiconductor manufacturing process, an overlay measurement instrument is used to inspect overlay accuracy after exposure. The overlay measurement results are not only used to evaluate accuracy, but also to optimize exposure processing by calculating various offsets based on the measurement results and feeding them back to the exposure system. Increasing the number of overlay measurement points can help identify and compensate for local distortions including EPE (edge placement errors). However, it is not practical to perform overlay measurement for all wafers and all regions, therefore the better strategy for is performing correction through combining predicted results with actual measurement results. Canon is working with Macronix to develop the VMOM (Virtual Machine Overlay Metrology) system for predicting overlay measurement results. The VMOM method uses machine learning to study large amounts of data to derive the relationship between overlay error results and exposure system process variables that cause overlay error. A VMOM model was developed using 3D-NAND process data and overlay prediction accuracy and exposure process optimization were evaluated. This paper reports the development status of the VMOM system and the practical effects of the system.
Semiconductor manufacturing equipment must maintain high productivity and provide high-yield processing and Canon has developing high-reliability exposure tools that have demonstrated high-uptime and performance stability in production. As global emergency epidemic restrictions limit the travel of expert engineers, customer service becomes more challenging and alternative methods of support are being developed to help customers meet their production roadmaps. To help control performance, lithography tools have sophisticated logging systems that can monitor every movement in the tool and we studied a novel Artificial Intelligence system that utilizes big logging data to help improve exposure tool uptime, productivity and performance related to yield. One goal of our study is to minimize exposure tool downtime by monitoring and reacting to tool status. For this purpose we are applying machine learning to develop abnormality detection or prediction models with automated recovery procedures for each abnormality. We will report on Auto-Fault-Tree-Analysis (FTA) models being constructed to evaluate large volumes of design and trouble information to help minimize downtime. Another study goal is to improve lithography tool performance by monitoring and reacting to factors including overlay accuracy and CD uniformity that can strongly affect device yield. Outputs of this analysis include simulation and optimization of equipment performance, and virtual metrology. This paper reports on the system we are developing to help increase the uptime, productivity and imaging performance of Canon semiconductor lithography tools. The system is designed to monitor the operating state of lithography tools and apply automated recovery and optimization actions identified through machine learning.
More-than-Moore approaches to improve system performance have been a hot topic for a more than a decade as a way to maximize the efficiency and increase the bandwidth of high performance computing systems. Fan-Out packaging that realizes submicron Redistribution Lines (RDL) and large die sizes is one technology that can help enable complex heterogeneous integration for applications including Artificial Intelligence (AI) and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool (stepper) capable of submicron resolution on 500 mm panels. The panel exposure tool is equipped with wide-field projection optics that offer a large 52 mm × 68 mm image field and a 0.24 NA that is optimum for submicron resolution. The stepper also features an updated panel handling system for processing up to 515 × 515 mm panels. In this paper, we will report on our study of fine patterning on rectangular panels using the submicron resolution panel stepper and will introduce technology innovations supporting advanced heterogeneous integration. Our study researched photoresist material performance and slit-coating uniformity challenges we identified through collaboration with resist vendors and slit-coating equipment manufacturers. We will report on the results of our collaborative study and will discuss current and future PLP advantages, challenges and solutions.
In recent years, the demand for high sensitivity image sensors has become prominent, in correlation with the reduction of
pixel size and higher pixel counts. Sensitivity is especially important for mobile applications and as a result, back side
illumination (BSI) structure image sensors are emerging.
The spread of BSI image sensors causes new technological challenges in the lithographic process. One of the challenges
is related to the wafer distortion created during the bonding and thinning of the wafer. The challenge is to reduce the
impact of the wafer distortion on the overlay accuracy, and we propose two unique solutions for this challenge: Extended
Advanced Global Alignment (EAGA) and Shot Shape Compensator (SSC). EAGA is an alignment measurement
function that can measure the position and shape of all shots on the wafer. SSC is an exposure function that adjusts the
shape of exposure shots according to the shape of the underlying layer's shot on the distorted wafer, by controlling both
the XY magnification difference and skew component of the projection optical system. In order to realize the SSC
system in i-line stepper, Canon has introduced a new compensation mechanism featuring “two-dimensional Alvarez”
optical elements.
One other challenge is to detect alignment marks located on the back surface of the silicon wafer and for this challenge,
Canon has employed a new alignment system using infrared light.
In this paper, we will provide detailed descriptions along with exposure results using these solutions. We will also delve
into the possibility of additional process applications that can benefit from the enhanced overlay accuracy provided by
Canon i-line lithography systems.
In recent years, demand for high-density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through-Silicon Via (TSV) technology, 2.5D integration technology using silicon interposers has also become a hot topic. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool (stepper) that is now in wide use at customer sites for their most challenging processes. In this paper, Canon will explain details of FPA-5510iV features that support high-density integration. Canon will also introduce additional challenges that must be solved to ensure the success of high-density integration technologies in mass production, as well as Canon efforts to solve the remaining challenges.
3D stacking technology using TSVs, as well as linewidth shrinking, is crucial for future progress in semiconductor
devices. A new i-line exposure tool, the FPA-5510iV, has been developed which provides the functions necessary for
implementing TSV processes. This paper reports on Canon's commitment to make advanced TSV processes a reality.
The 65nm and the subsequent 45nm node lithography require very stringent CD control. To realize high-accuracy CD
control on an exposure tool, it is essential to reduce wavefront aberrations induced by projection optics design and
manufacturing errors and then stabilize the aberrations while the exposure tool is in operation. We have developed two
types of new hyper-NA ArF projection optics to integrate into our new platform exposure tool: a dry system and a
catadioptric system for immersion application. In this paper, aberration measurement results of these projection
systems are shown, demonstrating that ultra-low aberration is realized. In addition, a new projection optical system has
been developed which incorporates high degree-of-freedom Aberration Controllers and automatic aberration measuring
sensors. These controllers and sensors are linked together through Aberration Solver, a software program to determine
optimal target values for aberration correction, thereby allowing the projection optics to maintain its best optical
properties. The system offers excellent performance in correcting aberrations that come from lens heating, and makes it
possible to guarantee extremely low aberrations during operation of the exposure tool.
We developed subhalf micron steppers, the FPA-2500i2 and the FPA-2500i3 (abbreviated here as i2 and i3, respectively), suitable to 16 M and 64 M DRAM processes. These new steppers incorporate high sensitivity reticle particle monitors (RPM) in order to increase chip yield. In this report, first the steppers' basic performance is demonstrated. Secondly, the printability of particles and its influence on circuit patterns are quantified by simulations and experiments. Thirdly, the RPM's detection principle is discussed theoretically, and finally the experimental results are shown.
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