Mr. Sheng-Tsung Tsao Profile

Sheng-Tsung Tsao

at Changxin Memory Technologies Inc

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Publications (5)

Proceedings Article | 26 May 2022 Poster + Paper

Computational metrology introduction into high volume manufacturing fab through 1x nm uDBO measurement and monitor

Chia Hung Chen, Wenkang Song, Hongwei Zhu, Sheng-Tsung Tsao, Jie Du

Proceedings Volume 12053, 120531M (2022) https://doi.org/10.1117/12.2612486

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, High volume manufacturing, Scanners, Data modeling, Stars, Lithography, Contamination, Optimization (mathematics)

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Proceedings Article | 22 February 2021 Poster + Presentation + Paper

Accuracy aware pixel selection in multi-wavelength uDBO metrology enables higher robustness and accuracy for DRAM

Chia Hung Chen, Sheng-Tsung Tsao, Jie Du, Wenkang Song, Hongwei Zhu, Ji-Ling Hou, Longfei Shen, Sunny Xia, Simon Mathijssen, Marc Noot, Farzad Farhadzadeh, Kimi Yang, Xing Ma, Zhi-Qiang Tang, Jing Wang, Yu Liu, David Xu, Herman Heijmerikx, Eason Su, Elliott Mc Namara, Kaustuve Bhattacharyya

Proceedings Volume 11611, 116112Z (2021) https://doi.org/10.1117/12.2583818

KEYWORDS: Metrology, Overlay metrology, High volume manufacturing, Front end of line, Detection and tracking algorithms

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Proceedings Article | 20 March 2020 Paper

New improving metrology for advanced memory devices with high transmission attenuated phase shift mask

Chia-Hung Chen, Sheng-Tsung Tsao, CongCong Fan, Jie Du, Richer Yang, Asei Chou, Kunyuan Chen, Jimmy Chang, JunJun Zhang, Wallace He, Leslie Zhang, YunSheng Xia

Proceedings Volume 11325, 113252U (2020) https://doi.org/10.1117/12.2552025

KEYWORDS: Optical alignment, Photomasks, Semiconducting wafers, Metrology, Phase shifts, Overlay metrology, Optical proximity correction, Diffraction

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Proceedings Article | 20 March 2020 Paper

Saving scribe-lane space by using narrow alignment marks

Chia-Hung Chen, Sheng-Tsung Tsao, CongCong Fan, Jie Du, Richer Yang, Asei Chou

Proceedings Volume 11325, 113252V (2020) https://doi.org/10.1117/12.2552027

KEYWORDS: Optical alignment, Semiconducting wafers, Light sources, Scanners, Signal detection, Reliability

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During wafer exposure, the scanner overlays product structures from the layer being exposed onto underlying layers, with a limited error margin. Alignment is the process of measuring pre-defined marks that have been exposed on previous layers and using these measurements to determine what adjustments to make during exposure. Current alignment marks are still quite big compared to overlay targets and fill quite some reticle-area. Therefore, there is a drive towards narrower and smaller alignment marks in order to free up scribe-lane space. Further, during design of narrower and/or smaller alignment marks, not only the width or length needs to be taken into account, but also the process loading effect and scribe-lane dummy following rules.

Maximizing product-area is an important driver for many DRAM customers. One way is by reducing scribe-lane space. Currently most customers are using 60um to 90 um wide scribe-lanes. However, developments are ongoing to further reduce this to 40um -50um. The current narrowest standard ASML alignment marks are 40 um wide and there is a growing demand for narrower and even smaller marks. Experiment tool groups configure selection with ASML SMASH senor and it brings more possibility in scribe-lane design and alignment size topic.

Tests with narrow alignment marks were done on an ASML XT1460K scanner with SMASH3.1 sensor. Both narrow DPCM (coarse align) and narrow NSSM marks (coarse and fine align) were tested and the impact on accuracy, repro and overlay was investigated. The width of the DPCM marks was reduced from 160um to 150um and 140um. The width of the NSSM (AA11 and AH53) marks was reduced from 40um to 30um and 28um.

This paper will explain the tests done in detail and will present the results of using narrow marks on alignment mark repro, mark KPIs (WQ, MCC, etc.) and overlay performance. These results will be compared to those of the standard marks. Also results from further alignment mark recipe optimization will be presented.

Proceedings Article | 20 March 2019 Paper

Robust alignment mark design for DRAM using a holistic computational approach

Danying Li, Stella Zhang, Chia-Huang Chen, Youping Zhang, Alex Huang, David Xu, Yufeng Wang, Zhen Shi, Shi-lu Wang, Sheng-Tsung Tsao, Angmar Li, Andy Yang, Junwei Lu

Proceedings Volume 10961, 109610Z (2019) https://doi.org/10.1117/12.2532841

KEYWORDS: Optical proximity correction, Optical alignment, Semiconducting wafers, Optical lithography, Signal processing, Printing, Metrology, Overlay metrology

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