In this paper we study the trade-offs and benefits of using ILT-based SRAF placement/OPC over conventional SRAF placement/OPC for various front-end and back-end design configurations on a full chip. We explore the use models and benefits of using ILT-based Local Printability Enhancement (LPE) in an automated flow to eliminate hot spots that can be present on the full chip after conventional SRAF placement/OPC. We study the impact on process-window, performance, and mask manufacturability.
Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage
of non-uniform reflective substrates without bottom anti-reflection coating (BARC).
Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer
topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects
such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without
BARC, e.g., implant layer, as technology node shrinks.
For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated
using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and
resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate
them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if
well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and
they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers
wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full
chip OPC on implant layers.
Since the sub-50nm logic lithography approaches to k1 value of 0.3, it seems to be an impossible task to print typical
logic patterns composed of random shapes and mixed pitches using the conventional resolution enhancement technology
(RET). As one of the effective solutions to deal well with this issue, lithography friendly design (LFD) and advanced
optical proximity correction (OPC) technology have been considered and developed. However, the investigation on the
distortion types of various 2-dimensional patterns has rarely been preceded up to now, while lithographical hot spots are
observed are dominated by the 2-dimensional patterns rather than in the 1-dimensional patterns. In order to provide a
LFD layout and a good OPC performance for the future node logic device, the analysis and the hot spot's classification
of the 2-dimensional pattern need to be performed. Based on our analysis of various pattern types at mimic-logic test
block, a feedback strategy was implemented to reduce the 2-dimensional hot spots through the correction stage of the
OPC recipes. In our study, we find out the proper value of ground rule and the cost-effective methodology which should
go with reciprocal encouragement in OPC and LFD. This will give us a good methodology for the lithography
technology nodes and upstream design for manufacturability (DFM) approaches.
The main object of this paper is to investigate the root cause of CD change by neighboring field observed in KrF scanner (max. 0.70NA) and to measure the amount of stray light from neighboring field precisely. Line widths of gate pattern are measured at the isolated and surrounded field and the amount of CD change by neighboring field is found to be proportional to the clear ratio of mask. By exposing with special configuration, it is found that the line width is linearly decreased as the dose of neighboring field increases. From this linear dependency on doses of neighboring field, it is clear that non-negligible amount of light is scattered out into the adjacent field. The amount of this stray light level coming from neighboring field is obtained quantitatively by synthetic analysis of above result and double exposure to mimic background DC light by flare. About 1.2% of stray light from outside of the field is observed at the slit position close to the boundary of neighboring field. Disappearing pad test is also performed to measure the flare from exposure of field itself. Finally, it is obtained the distribution of total stray light - nominal flare plus flare from adjacent field - and it is found to be existed around 0.7% deviation of stray light across the slit.
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