Scanning Electron Microscopy (SEM) technology makes use of an electron beam (e-beam) with wide energy range from 0.1 to 50 keV, so it is possible to measure wafers from surface to deep and buried structures. Due to its superior accuracy, it is widely used for in-line metrology and inspection (MI) process. As devices scaling down for performance enhancement, the MI process became inaccurate due to the target structure shrinkage and complicated electrons’ behavior inside it. To overcome the challenges, accurate simulation tool is required to understand its underlying mechanism theoretically. In this paper, we propose a unifying framework for simulating SEM operation by implementing Nebula e-beam computing algorithm on the Technology Computer-Aided Design (TCAD) environment. The proposed framework integrates various physics models including the scattering and transport behaviors of electrons, which enables to calculate the important trajectories of electrons in the most important regions of wafers. In addition, it gives an expandability on further integration thanks to the computability of TCAD environment. We validate the proposed framework with demonstrating key applications on real products.
In recent years, the overlay specifications of advanced semiconductor devices have become extremely stringent. This challenging situation becomes severe for every new generation of the device development. However, conventional overlay metrology systems have limited throughput due to their point-based nature. Here, we first demonstrate the novel imaging Mueller-matrix spectroscopic ellipsometry (MMSE) technique, which can measure the overlay error of all cell blocks on a device wafer with extremely high throughput, much faster than conventional point-based spectroscopic ellipsometry (SE) technologies. It provides the super large field of view (FOV) ~ 20 × 20 mm2 together with high sensitivity based on Mueller information, which will be truly innovated solution not only for the overlay metrology, but also for critical dimension (CD) measurement, eventually maximizing process control and productivity of advanced node.
In this paper, we propose an unique metrology technique for the measurement of three-dimensional (3D) nanoscale structures of semiconductor devices, employing imaging-based massive Mueller-matrix spectroscopic ellipsometry (MMSE) with ultra-wide field of view (FOV) of 20×20 mm2. The proposed system enables rapid measurement of 10 million critical dimension (CD) values from all pixels in the image, while the conventional point-based metrology technique only measures a single CD value. We obtain Mueller matrix (MM) spectrum by manipulating wavelength and polarization states using a custom designed optical setup, and show that the proposed method characterizes complex 3D structures of the semiconductor device. We experimentally demonstrate CD measurement performance and consistency in the extremely large FOV, and suggest that the combination of MMSE and massive measurement capability can provide valuable insights: fingerprints originated from the manufacturing process, which are not easily obtained with conventional techniques.
An innovative metrology technique has been devised to address current limitations of optical critical dimension (OCD) in advanced semiconductor metrology. This technique is based on multiple self-interferometric pupil imaging, called Mueller matrix self-interferometric pupil ellipsometry (M-SIPE). The system integrates an innovatively designed interference generator in both illuminating and imaging optics, allowing for the massive acquisition of full polarization information across entire angles around the device. The vast amount of information can offer fully comprehensive structural analysis, accomplishing enhanced sensitivity and the ability to break the well-known parameter correlation issues. The system employs a single-shot holographic measurement technique on the pupil plane, enabling rapid acquisition of three-dimensional spectral information, such as wavelengths, incidence angles, and azimuth angles. Thus, unlike conventional OCD tools, M-SIPE can obtain multi-angular and full polarization information without any mechanical movements. We verified the performance of M-SIPE by the experiment of non-patterned wafers of various conditions using an optical testbed. Our results confirmed good agreement between the experiment and theoretical simulations across all angular ranges. Furthermore, the actual device simulation was conducted to show sensitivity enhancement and ability for breaking the parameter correlation issues. The results confirmed that the large amount of angular information from M-SIPE technique could overcome current metrological challenges.
Ruthenium (Ru) film used as capping layer in extreme ultraviolet (EUV) mask peeled off after annealing and in-situ UV (IUV) cleaning. We investigated Ru peeling and found out that the mechanical stress caused by the formation of Si oxide due to the penetration of oxygen atoms from ambient or cleaning media to top-Si of ML is the root cause for the problem. To support our experimental results, we developed a numerical model of finite element method (FEM) using commercial software (ABAQUS™) to calculate the stress and displacement forced on the capping layer. By using this model, we could observe that the displacement agrees well with the actual results measured from the transmission electron microscopy (TEM) image. Using the ion beam deposition (IBD) tool at SEMATECH, we developed four new types of alternative capping materials (RuA, RuB, B4C, B4C-buffered Ru). The durability of each new alternative capping layer observed by experiment was better than that of conventional Ru. The stress and displacement calculated from each new alternative capping layer, using modeling, also agreed well with the experimental results. A new EUV mask structure is proposed, inserting a layer of B4C (B4C-buffered Ru) at the interface between the capping layer (Ru) and the top-Si layer. The modeling results showed that the maximum displacement and bending stress observed from the B4C-buffered Ru are significantly lower than that of single capping layer cases. The durability investigated from the experiment also showed that the B4C-buffered structure is at least 3X stronger than that of conventional Ru.
In EUV Lithography, an absence of promising candidate of EUV pellicle demands new requirements of EUV mask cleaning which satisfy the cleaning durability and removal efficiency of the various contaminations from accumulated EUV exposure. It is known that the cleaning with UV radiation is effective method of variety of contaminants from surface, while it reduces durability of Ru capping layer. To meet the expectation of EUV mask lifetime, it is essential to understand the mechanism of Ru damage. In this paper, we investigate dominant source of Ru damage using cleaning method with UV radiation. Based on the mechanism, we investigate several candidates of capping to increase the tolerance from the cycled UV cleaning. In addition, we study durability difference depending on the deposition method of Ru capping. From these studies, it enables to suggest proper capping material, stack and cleaning process.
In EUVL, major impacts on determining critical dimension (CD) are resist process, scanner finger print, and mask characteristics. Especially, reflective optics and its oblique incidence of light bring a number of restrictions in mask aspect. In this paper, we will present one of the main contributors for wafer CD performance, such as center wavelength (CW) of multilayer (ML) in EUVL mask. We evaluate wafer CDs in 27.5nmHP L/S, 30nmHP L/S, and 30nmHP contact patterns with NXE3100 by using masks with purposely off-targeted CW ranging from 13.4 to 13.7nm. Based on the results from the exposure experiments, we verify that the CW specification for NXE3100 is regarded as 13.53 ± 0.015nm at CWU=0.03nm to satisfy the wafer CD requirements. According to verified simulations, however, we suggest a new CW specification for NXE3300 with higher values considering wide illumination cone angle from larger numerical aperture (0.33NA). Moreover, simulations in different exposure conditions of NXE3300 with various patterns below 20nm node show that customized CW specification might be required depending on target layers and illumination conditions. We note that it is also important to adjust CW and CWU in final mask product considering realistic difficulties of fabrcation, resulting in universal CW specification.
Reduced design rules demand higher sensitivity of inspection, and thus small defects which did not affect printability
before require repair now. The trend is expected to be similar in extreme ultraviolet lithography (EUVL) which is a
promising candidate for sub 32 nm node devices due to high printing resolution. The appropriate repair tool for the small
defects is a nanomachining system. An area which remains to be studied is the nano-machining system performance
regarding repair of the defects without causing multilayer damage. Currently, nanomachining Z-depth controllability is 3
nm while the Ru-capping layer is 2.5 nm thick in a Buffer-less Ru-capped EUV mask. For this report, new repair
processes are studied in conjunction with the machining behavior of the different EUVL mask layers. Repair applications
to achieve the Edge Placement(EP) and Z-depth controllability for an optimal printability process window are discussed.
Repair feasibility was determined using a EUV micro exposure tool (MET) and Actinic Imaging Tool (AIT) to evaluate
repairs the 30 nm and 40 nm nodes. Finally, we will report the process margin of the repair through Slitho-EUVTM
simulation by controlling side wall angle, Z-depth, and EP (Edge Placement) on the base of 3-dimensional experimental
result.
Nano-machining repair tool plays an important role in the current 65 nm node photomask repair. It
removes defects mechanically with nanometer sized diamond tip with high accuracy and low damage using
high accuracy AFM data. The repair performance of nano-machining repair system largely depends on the
diamond tip whose aspect ratio decides the minimum reparable feature size. As the device shrinks to 45 nm
or 32 nm node, higher aspect ratio tip with weak structure is required. It is contradiction to the fact that
more accurate edge placement and better repair slope is required in smaller node repair, because deflection
or tip wear effect could happen in high aspect ratio tip. In this article, deflection and wear effect were
investigated in single layer repair recipe using SEM and AIMSTM. Multilayer recipe which complements
weak structure was estimated carefully, and some limits were discussed. Finally some requirements of
nano-machining repair system for 45 nm node were presented.
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