KEYWORDS: Optical proximity correction, Photomasks, Waveguides, Photonic devices, Lithography, Line edge roughness, Stochastic processes, Photonics, Signal to noise ratio
Photonics represents a growing opportunity to design and manufacture devices and integrated circuits for applications in high-speed data communications, advanced sensing, and imaging. Photonic technologies provide orders-of-magnitude speed improvements with reduced power consumption for data transmission and ultra-sensitive sensing capabilities in multiple application domains. Curvilinear patterns are required to maintain the physical properties of light propagation. We investigate the readiness of state-of-the-art mask synthesis tools to meet the challenges for photonics devices in terms of mask data preparation and verification. We apply OPC and ILT to photonic integrated circuit designs containing components sensitive to fabrication variation, to generate Manhattan and curvilinear mask data. Results are validated using a lithography verification tool considering smoothness of the printed curved structures, a key factor to maintain the correct functionality of the photonic devices. Rather than using ideal targets, we take simulation contours from corrected layouts for initial assessment of light propagation through wave guides. The impact of lithographic patterning related perturbations such as resist line edge roughness on optical performance is investigated based on results from a rigorous lithography process simulation model. Experimental data from fabricated devices underline the usefulness of lithography simulation to predict unwanted impact on device performance and the need of correction tools to counteract these effects.
During early stage development of a DSA process, there are many unknown interactions between design, DSA process,
RET, and mask synthesis. The computational resolution of these unknowns can guide development towards a common
process space whereby manufacturing success can be evaluated. This paper will demonstrate the use of existing Inverse
Lithography Technology (ILT) to co-optimize the multitude of parameters.
ILT mask synthesis will be applied to a varied hole design space in combination with a range of DSA model parameters
under different illumination and RET conditions. The design will range from 40 nm pitch doublet to random DSA
designs with larger pitches, while various effective DSA characteristics of shrink bias and corner smoothing will be
assumed for the DSA model during optimization. The co-optimization of these design parameters and process
characteristics under different SMO solutions and RET conditions (dark/bright field tones and binary/PSM mask types)
will also help to provide a complete process mapping of possible manufacturing options. The lithographic performances
for masks within the optimized parameter space will be generated to show a common process space with the highest
possibility for success.
This work presents how the combination of EDA and CDSEM tools enable development and manufacturing engineers to collect CDSEM data of a large diversity of features and contexts seamlessly for OPC model calibration and validation, process development, and inline manufacturing monitoring. We will present the application and results of a solution proposed in a previously published paper[1] and then review the benefits of enabling development and manufacturing engineers to make metrology-related decisions within their environments. Finally, new applications for automated CDSEM recipe generation and data collection will be discussed.
This work presents software tools that enable engineers to make relevant SEM measurement decisions in the EDA
environment, presented in the optimal context for the engineer, and pass them seamlessly into the SEM environment. We
present the tools and interfaces leveraged in this solution and explore the benefits of enabling OPC modeling engineers
to make metrology-related decisions within the OPC environment. New opportunities for automation of metrologyrelated
OPC tasks are also discussed.
Lithography development has become extremely computationally intensive. For a particular technology node
being developed, it is critical to determine the optimum source and OPC/RET for each layer. In this paper we
present a flexible new computation system for automation of source, OPC and RET optimization of advanced lithography layers. Of course, before determining the optimum source/RET/OPC of any layer, it is equally critical to determine the design rules which can be manufactured at a particular technology node. The design rule computational lithography problem is a superset of the source/OPC/RET optimization problem. With an automated methodology, time for process development can be reduced dramatically if a process development engineer can determine the design rules through accurate, automated simulation of the entire flow.
A new method for simultaneous Source-Mask Optimization (SMO) is presented. In order to produce optimum
imaging fidelity with respect to exposure lattitude, depth of focus (DoF) and mask error enhancement factor
(MEEF) the presented method aims to leverage both, the available degrees of freedom of a pixelated source
and those available for the mask layout. The approach described in this paper is designed as to work with
dissected mask polygons. The dissection of the mask patterns is to be performed in advance (before SMO) with
the Synopsys Proteus OPC engine, providing the available degrees of freedom for mask pattern optimization.
This is similar to mask optimization done for optical proximity correction (OPC). Additionally, however, the
illumination source will be simultaneously optimized. The SMO approach borrows many of the performance
enhancement methods of OPC software for mask correction, but is especially designed as to simultaneously
optimize a pixelated source shape as nowadays available in production environments. Designed as a numerical
optimization approach the method is able to assess in acceptable times several hundreds of thousands source-mask
combinations for small, critical layout snippets. This allows a global optimization scheme to be applied to the
SMO problem which is expected to better explore the optimization space and thus to yield an improved solution
quality compared to local optimizations methods. The method is applied to an example system for investigating
the impact of source constraints on the SMO results. Also, it is investigated how well possibly conflicting goals
of low MEEF and large DoF can be balanced.
Source mask optimization is becoming increasingly important for advanced lithography nodes.
In this paper, we present several source mask optimization flows, with increasing levels of
complexity. The first flow deals with parametric source shapes. Here, for every candidate
source, we start by placing model-based assist features using inverse mask technology (IMT).
We then perform a co-optimization of the main feature (for OPC) and assist feature (for
printability). Finally, we do a statistical analysis of several lithography process metrics to
determine the quality of the solution, which can be used as feedback to determine the next
candidate source. In the second flow, the parametric source is instead approximated by a pixel
based source inverter, providing a fast and efficient way of exploring the source solution space.
The final flow consists of pixilated source shapes realizable via DOEs or programmable
illumination.
Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.
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