Integrate LEDs and CMOS circuits on large Si wafers can enable numerous new applications and add new functions to Si integrated circuits. In the past efforts on the integration of AlGaInP LEDs and CMOS circuits on 200 mm Si wafers, we have solved fundamental problems such as III-V semiconductor heteroepitaxy on Si substrates, wafer bow control, and bonding of LED wafers with CMOS wafers. Our latest achievement in this work is the demonstration of working devices processed on 200 mm LED wafers. We will present our efforts on the development of CMOS-compatible Ohmic contacts, 200 mm wafer-scale processing, and characteristics of the devices. We have evaluated different metals as CMOS-compatible low-resistance Ohmic contacts to the AlGaInP LEDs. We will compare the performance of the LEDs using the different metal contacts. We will present our progress on the process of CMOS-bonded LED wafers. Different from the LED-only wafers, the process of CMOS-bonded LED wafers can only be done in opened trenches, which adds extra difficulties. In addition, we will show the method we have developed for the re-entry of the CMOS-LED integrated wafers to the CMOS foundries for the end-of-line metal interconnections. Finally, potential applications using the CMOS-integrated LEDs will be discussed.
The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.
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