The thin nature of EUV (Extreme Ultraviolet) resist has posed significant challenges for etch processes. In particular, EUV patterning combined with conventional etch approaches suffers from loss of pattern fidelity in the form of line breaks. A typical conventional etch approach prevents the etch process from having sufficient resist margin to control the trench CD (Critical Dimension), minimize the LWR (Line Width Roughness), LER (Line Edge Roughness) and reduce the T2T (Tip-to-Tip). Pre-etch deposition increases the resist budget by adding additional material to the resist layer, thus enabling the etch process to explore a wider set of process parameters to achieve better pattern fidelity. Preliminary tests with pre-etch deposition resulted in blocked isolated trenches. In order to mitigate these effects, a cyclic deposition and etch technique is proposed. With optimization of deposition and etch cycle time as well as total number of cycles, it is possible to open the underlying layers with a beneficial over etch and simultaneously keep the isolated trenches open. This study compares the impact of no pre-etch deposition, one time deposition and cyclic deposition/etch techniques on 4 aspects: resist budget, isolated trench open, LWR/LER and T2T.
Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.
KEYWORDS: Etching, Line edge roughness, Optical lithography, Back end of line, Chemistry, Front end of line, Lithography, Ions, Amorphous silicon, Extreme ultraviolet
Critical back end of line (BEOL) Mx patterning at 7nm technology node and beyond requires sub-36nm pitch line/space pattern in order to meet the scaling requirements. This small pitch can be achieved by either extreme ultraviolet (EUV) lithography or 193nm-immersion-lithography based self-aligned quadruple patterning (SAQP). With enormous challenges being faced in production readiness of EUV lithography, SAQP is expected to be the front up approach for Mx grid patterning for most of industry. In contrast to the front end of line (FEOL) fin patterning, which has successfully deployed SAQP approach since 10nm node technology, BEOL Mx SAQP is challenging owing to the required usage of significantly lower temperature budgets for film stack deposition. This has an adverse impact on the material properties of the as-deposited films leading to emergence of several challenges for etch including selectivity, uniformity and roughness.
In this presentation we will highlight those unique etch challenges associated with our BEOL Mx SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries & process steps for meeting the 7nm technology node targets. We will present comparison data on both organic and in-organic mandrel stacks with respect to LER/LWR & CDU. With LER being one of the most critical targets for 7nm BEOL Mx, we will outline our actions for optimization of our stack including resist material, mandrel material, spacer material and others. Finally, we would like to update our progress on achieving the target LER of 1.5 nm for 32nm pitch BEOL SAQP pattern.
EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.
Line edge roughness (LER) and line width roughness (LWR) are analyzed based on the frequency domain 3σ LER characterization methodology during pattern transfer in a self-aligned double patterning (SADP) process. The power spectrum of the LER/LWR is divided into three regions: low frequency, middle frequency, and high frequency regions. Three standard deviation numbers are used to characterize the LER/LWR in the three frequency regions. Pattern wiggling is also detected quantitatively during LER/LWR transfer in the SADP process.
A frequency domain 3 sigma LER characterization methodology combining the standard deviation and power spectral density (PSD) methods is proposed. In the new method, the standard deviation is calculated in the frequency domain instead of the spatial domain as in the conventional method. The power spectrum of the LER is divided into three regions: low frequency (LF), middle frequency (MF) and high frequency (HF) regions. The frequency region definition is based on process visual comparisons. Three standard deviation numbers are used to characterize the LER in the three frequency regions. Pattern wiggling can be detected quantitatively with a wiggling factor which is also proposed in this paper.
As feature critical dimension (CD) shrinks towards and beyond the 7nm node, patterning techniques for optical lithography with double and triple exposure will be replaced by EUV patterning. EUV enables process and overlay improvement, as well as a potential cost reduction due to fewer wafer passes and masks required for patterning. However, the EUV lithography technique introduces newer types of resists that are thinner and softer compared to conventional 193nm resists currently being used. The main challenge is to find the key etch process parameters to improve the EUV resist selectivity, reduce LER and LWR, minimize line end shrink, improve tip-to-tip degradation, and avoid line wiggling while still enabling previous schemes such as trench-first-metal-hard-mask (TFMHM), self-aligned via (SAV) and self-aligned contact (SAC).
In this paper, we will discuss some of the approaches that we have investigated to define the best etch process adjustments to enable EUV patterning. RF pulsing is one of the key parameters utilized to overcome most of the previously described challenges, and has also been coupled with stack optimization. This study will focus on RF pulsing (high vs. low frequency results) and bias control (RF frequency dependence). In particular, pulsing effects on resist morphology, selectivity and profile management will be reported, as well as the role of aspect ratio and etch chemistry on organic mask wiggling and collapse.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.
In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
The successful demonstration of 637 wafer exposures in 24 hours on the EUV scanner at the IBM EUV Center for
Excellence in July marked the transition from research to process development using EUV lithography. Early process
development on a new tool involves significant characterization, as it is necessary to benchmark tool performance and
process capability. This work highlights some key learning from early EUV process development with a focus on
identifying the largest sources of variability for trench and via hole patterning through the patterning process. The EUV
scanner demonstrated stable overlay on a 40 lot test run using integrated wafers. The within field and local critical
dimension uniformity (CDU) are the largest contributors to CD variations. The line edge roughness (LER) and line
width roughness (LWR) in EUV resist will be compared to the post etch value to determine the effect of processing.
While these numbers are generally used to describe the robustness of 1D trenches or circular vias, the need to accurately
evaluate the printability of irregular 2D features has become increasingly important. In the past 5 years, models built
from critical dimension scanning electron microscope (CDSEM) contours has become a hot topic in computational
lithography. Applying this methodology, the CDSEM contour technique will be used to assess the uniformity of these
irregular patterns in EUV resist and after etching. CDSEM contours also have additional benefits for via pattern
characterization.
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