EUV lithography has been brought into mass production. To enhance the yield, improvements in critical dimension (CD) stability, and defectivity still remain of utmost importance. In order to enhance the defectivity performance on contact hole pattern, continuous work has been executed.1 As the result of process optimizations presented at SPIE 2018 for 24 nm contact hole half pitch pattern, single- and multi-closed hole modes as caused by particles included in coating materials, called “in-film particles”, or stochastic failures are the major of defects modes. For defectivity improvement work done this year, optimization of material dispense has been carried out in an attempt to improve the defectivity of single- and multi-closed holes as caused by in-film particles. As the result, totally 19 % of defectivity improvement was obtained as compared with conventional dispense conditions. On the other hand, CD variability is comprised of several components such as wafer to wafer, field to field, within field, and local CD. In addition, not only coater/developer but also scanner, mask, and materials contribute to the variations. In this paper, CD uniformity (CDU) optimization on also contact hole 24 nm half pitch pattern has been executed to improve each component from the standpoint of coater/developer. As a result of the optimization of development process, 13.9 and 6.4 % of field to field and within field CDU improvement have been achieved, respectively.
It is important to remove image noise properly to measure critical dimension (CD) and roughness values from scanning electron microscope (SEM) images. In order to reduce image noise, the number of electron beam (EB) scans, or frame number, is increased. However, this excess EB irradiation damages the objects being measured and changes their size. In this paper, a new image analysis method is introduced to remove image noise without a typical noise filter. In this method, each image frame is used in a four dimensional array, and several artificial images are generated and edge coordinates are calculated. As a result of this new method, we can separate the line width roughness (LWR) components into process roughness and image noise, and analyze images with lower number of frames with minimal EB damage.
The impact of image noise on the accuracy of CD extraction is explained in the section on analysis of variance (ANOVA). The variation is separated as wafer to wafer (WTW), field to field (FTF), die to die (DTD), pattern to pattern (PTP), line width roughness (LWR), and stochastic pattern noise (SPN; which is random variation per a pattern) at this ANOVA. Roughness component from image noise is included in SPN. It is possible to remove the image noise component from SPN by applying this new image analysis method, and it is also possible to discuss the SPN from shot noise of exposure tool or variation of resist material component. ANOVA can put an end to discussion of measurement length of line pattern to know the state of low frequency roughness. LWR component of long wavelength is distributed to PTP and SPN when short patterns are measured. It is important to remove image nose properly and to compare the statistical analysis processed SPN value.
Multi-patterning, like LE and SAMP, has been in production for several years. It is expected to remain a standard in patterning, even in the case where industry adopts EUV photo lithography. As scaling continues, the precision of pattern placement remains challenging.
Edge Placement Error (EPE) has been proposed to define the requirements of a patterning process. Many authors have created statistical models for EPE, and gathered statistical data for CD and overlay (OVL), to make predictions about future technology specifications1-5. This work makes the following contributions:
Emphasis on large amount (63K) of on-product measurements
Use of ANOVA table to assess the hypothesis that a contender process is better than a POR process To differentiate our work, we have used the stochastic variable IPFE (Interactive Pattern Fidelity Error), which is an indicator to quantify the quality of on-wafer edge placement accuracies in multi-patterning6. In our previous paper, we have studied how overlay, LCDU and pitch walk factor into the IPFE budget7. In this work, we focus on experimental verification of the expected relationships between LCDU, overlay and CD variation, applied to the case of SADP (block on spacer):
We re-confirm that population ‘blocks-on-gap’ have a worse IPFE performance than ‘block-on-core’
We determine experimental behavior of IPFE vs line CD, block CD, and overlay (w/o assumption for any model) From this exercise, we can conclude that this IPFE indicator is a robust metric for the managing quality of any integrated patterning scheme.
EUV lithography will to be brought into mass production soon. To enhance the yield, improvements in critical dimension (CD) stability, and defectivity still remain of utmost importance. In order to enhance the defectivity ability on contact hole (CH) pattern, continuous work has been executed.1 On 24 nm contact hole half pitch pattern, residue and single-closed hole modes still remain the majority of defects. The main cause of residue defects is that water droplets from the rinse process, in which resist components are absorbed, are dried out on the wafer leaving a remaining residue. While probable causes of single-closed hole are particles included in the coating material or stochastic failures. To reduce the residue defect counts and single-closed hole as caused by in-film particles, optimization of rinse process and material supply system have been carried out. As the result, 97 % of residue defect reduction and 73 % of single-closed hole defect improvement have been achieved as compared with conventional processes. On the other hand, not only coater/developer but also EUV scanner, mask, resist, etc. contribute to the CD variation.1 Global CD uniformity (CDU) is comprised of several components such as wafer-to-wafer CDU, field-to-field one, withinfield one. In this paper, optimization of development processes has been executed to improve field-to-field and within field CDU components. As a result of the optimization, 14 and 6.4 % of field-to-field and within-field CDU improvement have been achieved, respectively.
Photosensitized Chemically Amplified ResistTM (PSCARTM) **2.0’s advantages and expectations are reviewed in this paper. Alpha PSCAR in-line UV exposure system (“Litho Enhancer”) was newly installed at imec in a Tokyo Electron Ltd. (TELTM)’s CLEAN TRACKTM LITHIUS ProTM Z connected to an ASML’s NXE:3300. Using the Litho Enhancer, PSCAR 2.0 sensitization preliminary results show that suppression of roughness enhancement may occur while sensitivity is increased. The calibrated PSCAR 2.0 simulator is used for prediction of resist formulation and process optimization. The simulation predicts that resist contrast enhancement could be realized by resist formulation and process optimization with UV flood exposure.
Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. One of the initial layers to be printed with EUV will be contact hole, therefore, we are concentrating on the productivity improvements of that layer.
In our report at SPIE 2017, defect reduction was achieved using the latest rinse technology in the development process and in-film defectivity was improved with material dispense optimization on a 24 nm contact hole (CH) pattern. On the basis of the knowledge acquired from the previous evaluation, improvements have been taken a step further in this next evaluation. As a result, 96% of residue defect reduction and 42% of in -film particle defect reduction has been achieved by further rinse optimization and improvement of dispense system.
For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15% of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.
In the discussion of edge placement error (EPE), we proposed interactive pattern fidelity error (IPFE) as an indicator to judge pass/fail of integrated patterns. IPFE consists of lower and upper layer EPEs (CD and center of gravity: COG) and overlay, which is decided from the combination of each maximum variation. We succeeded in obtaining the IPFE density function by Monte Carlo simulation. In the results, we also found that the standard deviation (σ) of each indicator should be controlled by 4.0σ, at the semiconductor grade, such as 100 billion patterns per die. Moreover, CD, COG and overlay were analyzed by analysis of variance (ANOVA); we can discuss all variations from wafer to wafer (WTW), pattern to pattern (PTP), line edge roughness (LWR) and stochastic pattern noise (SPN) on an equal footing. From the analysis results, we can determine that these variations belong to which process and tools. Furthermore, measurement length of LWR is also discussed in ANOVA. We propose that the measurement length for IPFE analysis should not be decided to the micro meter order, such as >2 μm length, but for which device is actually desired.
Extreme ultraviolet lithography (EUVL) technology is getting closer to high volume manufacturing phase every year. In order to enhance the yield of EUV lithography processing, further improvement of defectivity and CD uniformity is required at the moment. In our previous report in 2017, we have exhibited the defectivity reduction by applying our new rinse and dispense system to a 24nm contact hole (CH) pattern. On the basis of the knowledge received through that evaluation, further study for improvement of the defectivity has been investigated in this paper. As a result of further optimization of the rinse process, 83 % further reduction of residue defect from the result reported previously is achieved. Also, CD uniformity control is a very crucial factor towards EUVL manufacturing phase. We have exposed 15 wafer batches continuously for both line/space and contact hole patterns in order to confirm the current status of wafer to wafer (WTW) as well as field to field (FTF), die to die (DTD), and local uniformity. Now further work for improving CD stability is ongoing based on the results from this first trial.
Extreme ultraviolet lithography (EUVL) technology is getting closer to high volume manufacturing phase every year. In order to enhance the yield in EUV lithography process, further improvement of defectivity is required at the moment. In this paper, optimized rinse and new dispense system (NDS) have been applied to a 24nm contact hole (CH) pattern in order to achieve defect reduction. As a result, the optimized rinse reduced approximately 70 % of residue defects. In addition, NDS for coating process exhibited 80 % defect reduction in particles in the coating films of material such as SOC, SOG, and resist.
In our previous paper dealing with multi-patterning, we proposed a new indicator to quantify the quality of final wafer pattern transfer, called interactive pattern fidelity error (IPFE). It detects patterning failures resulting from any source of variation in creating integrated patterns. IPFE is a function of overlay and edge placement error (EPE) of all layers comprising the final pattern (i.e. lower and upper layers). In this paper, we extend the use cases with Via in additional to the bridge case (Block on Spacer). We propose an IPFE budget and CD budget using simple geometric and statistical models with analysis of a variance (ANOVA). In addition, we validate the model with experimental data. From the experimental results, improvements in overlay, local-CDU (LCDU) of contact hole (CH) or pillar patterns (especially, stochastic pattern noise (SPN)) and pitch walking are all critical to meet budget requirements. We also provide a special note about the importance of the line length used in analyzing LWR. We find that IPFE and CD budget requirements are consistent to the table of the ITRS’s technical requirement. Therefore the IPFE concept can be adopted for a variety of integrated structures comprising digital logic circuits. Finally, we suggest how to use IPFE for yield management and optimization requirements for each process.
Challenges of processing metal containing materials need to be addressed in order apply this technology to Behavior of metal containing materials on coater/developer processing including coating process, developer process and tool metal contamination is studied using CLEAN TRACKTM LITHIUS ProTM Z (Tokyo Electron Limited). Through this work, coating uniformity and coating film defectivity were studied. Metal containing material performance was comparable to conventional materials. Especially, new dispense system (NDS) demonstrated up to 80% reduction in coating defect for metal containing materials. As for processed wafer metal contamination, coated wafer metal contamination achieved less than 1.0E10 atoms/cm2 with 3 materials. After develop metal contamination also achieved less than 1.0E10 atoms/cm2 with 2 materials. Furthermore, through the metal defect study, metal residues and metal contamination were reduced by developer rinse optimization.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.