With the integration and design complexity of silicon photonics chips raises, the cost of manual routing based on design experience has significantly increased, which brings urgent demand for auto routing methods. This article proposed a global auto routing method for single waveguide connection in photonic integrated circuits. The method firstly partitions all routable areas into non-uniform grids based on the layout placement information and converts the grids into an undirected graph with respect to the path length and congestion of waveguides between adjacent grids. Next, an improved A* algorithm runs in the graph to find a best path between two optical ports, with additional penalties on every bend in the path, beyond cumulative lengths and congestion penalties. Heuristic terms have also been added to increase the convergence speed of the algorithm. The optimized path in graph is further used to perform multiple adhesive lines for waveguide control points generation. Then, three types of 90-degree bends and two types of S-bend according to specific spacing and angle relationships between control points are applied to generate waveguide trace. This method can avoid collisions between target waveguide and other devices on the layout, optimize the global path length, minimize the number of waveguide’s bends, prevent waveguide congestion in specific spaces from exceeding the set threshold, and at the same time generate the optimal waveguide and insert it into layout.
This article presents a graph-driven placement framework for Si photonic circuits. In this framework, a netlist exported from the schematic diagram is transferred into an adjacency matrix, and further parameterized to an undirected graph. By this method, optical devices and waveguides are quantified as nodes and edges, respectively. Non-Euclidean data structures between nodes can be extracted which includes parallel relations, sequential relations and connecting patterns, by matching those patterns with pre-defined database, certain layout strategies formulated by human experts can be properly applied. By extracting the geometric information and the preset spacing requirements of each device in the Process Design Kit library, the layout strategy requirements of each component can be assigned, so as to determine the geometric position. This work designed the graph-driven placement framework, tested the identification accuracy for connection pattern, and applied the framework in practical chip designs including artificial intelligent and Wavelength Division Multiplexing circuits.
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