Presentation + Paper
1 May 2017 An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems
Author Affiliations +
Abstract
Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA’s lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Omer Gunay, Ismail Ozsarac, and Fatih Kamisli "An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems", Proc. SPIE 10223, Real-Time Image and Video Processing 2017, 102230G (1 May 2017); https://doi.org/10.1117/12.2262550
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KEYWORDS
Video

Video compression

Field programmable gate arrays

Computer programming

Video processing

Video coding

Video acceleration

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