FPGA-based transformable coprocessor for MPEG video processing

Hoi Chow; Hussein M. Alnuweiri

doi:10.1117/12.255829

21 October 1996 FPGA-based transformable coprocessor for MPEG video processing

Hoi Chow, Hussein M. Alnuweiri

Proceedings Volume 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic; (1996) https://doi.org/10.1117/12.255829
Event: Photonics East '96, 1996, Boston, MA, United States

Abstract

This paper demonstrates how an FPGA-based transformable coprocessor can be used to implement a real-time MPEG-1 video decoder with enhanced features. The transformable coprocessor consists of an FPGA, local static RAM, and a host bus interface built into the FPGA. The gate-limited FPGA core is reconfigured frequently to implement various parts of the video decoding process in real-time. Our results show that, through reconfiguration, FPGA-based processors can handle complex tasks (such as high-quality video decoding) adequately. We also identify the major bottlenecks that impede achieving higher speedups with the FPGAs. For MPEG-1 video processing, the major slowdown is caused by the excessive data transfers and bottlenecks due to bus interfaces and lack of sufficient storage in FPGA.

Citation Download Citation

Hoi Chow and Hussein M. Alnuweiri "FPGA-based transformable coprocessor for MPEG video processing", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255829

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