Region of Interest (ROI) readout is used in readout integrated circuit (ROIC) to improve the frame rate, and reduce the bandwidth for image sensor and infrared Focal Plane Array (IRFPA). The scheme of gray code addressing with the 64×1 minimum size of ROI is widely used. However, the circuit needs to be custom redesigned when the pixel array is changed, which reduces the scalability. The pixel scheme reduces the minimum size of ROI to 1×1. Because of its repeatable circuit design, the scheme has good scalability. But this program occupies the area of pixels, which reduces the dynamic range of image. In this paper, a ROI readout scheme using unit circuit for IRFPA is presented. The minimum size of ROI is reduced to 1×1 in the scheme without occupying the area of pixel. In order to achieve high scalability, reusable circuit named unit circuit is used to control the gating of pixels. The circuit design and simulation results are presented in this paper.
This paper presents a logarithmic response burst mode IRFPA ROIC with pixel level integration of BDI structure and memory cells. BDI structure provides stable bias for the detector, and converts detector current into logarithmic voltage fast. On-chip high speed video record is achieved by high speed sampling the logarithmic response voltage and storing it into the memory cells in order. A column level SAR ADC is used to convert the outputs of memory cells into digital code. The prototype chip with 64×64 pixels was designed and fabricated. Ultra-high speed video capturing at 1Mfps with 100 consecutive frames is successfully demonstrated.
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