The design of image low-pass filter ASIC architecture based on stochastic computing

Xueru Zhao; Guoqiang He; Kejun Ge

doi:10.1117/12.3030309

5 June 2024 The design of image low-pass filter ASIC architecture based on stochastic computing

Xueru Zhao, Guoqiang He, Kejun Ge

Proceedings Volume 13163, Fourth International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024); 131631A (2024) https://doi.org/10.1117/12.3030309
Event: International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024), 2024, Xi'an, China

Abstract

The image low-pass filter is an effective solution for denoising and improving image quality. The stochastic computing is a novel method for number representation and calculation in stochastic domain. Aiming at the problem of large computing resources and low operation speed in image low-pass filter processing, in this paper, a parallel ASIC architecture of image low-pass filter based on stochastic computing proposed, which effectively improves processing speed and reduces resource consumption. When the length of the probability domain is 128bits, compared with the traditional architecture, the computational gate resources are reduced by about 30% and the execution time is reduced by about 75% in the case of comparable processing performance.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Xueru Zhao, Guoqiang He, and Kejun Ge "The design of image low-pass filter ASIC architecture based on stochastic computing", Proc. SPIE 13163, Fourth International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024), 131631A (5 June 2024); https://doi.org/10.1117/12.3030309

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KEYWORDS

Image processing

Linear filtering

Computer architecture

Image filtering

Parallel computing

Design

Stochastic processes

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