Noise analysis of an 0.8-V ultralow-power CMOS operational amplifier

Chuang Zhang; Ashok Srivastava; Pratul Ajmera

doi:10.1117/12.488938

12 May 2003 Noise analysis of an 0.8-V ultra-low power CMOS operational amplifier

Chuang Zhang, Ashok Srivastava, Pratul Ajmera

Proceedings Volume 5113, Noise in Devices and Circuits; (2003) https://doi.org/10.1117/12.488938
Event: SPIE's First International Symposium on Fluctuations and Noise, 2003, Santa Fe, New Mexico, United States

Abstract

Noise due to back-gate forward bias between substrate and source of a MOSFET is analyzed and simulated. Noise level is compared between two CMOS circuits with and without back-gate forward bias. It is found that the output noise introduced by the back-gate forward bias method is only a few nV/square root (Hz), which only slightly increases the device noise. A CMOS op-amp is designed utilizing back-gate forward bias technique utilizing a level shift current mirror for operation at ultra low-power in μW range. The designed amplifier dissipates power of 40 uW and operates at ± 0.4 V to achieve a gain of 77 dB. The noise in ultra low-power op-amp is also investigated. The total output noise density is about 30 μV/square root (Hz) in the ultra-low power op-amp design, which is lower than 65 μV/square root (Hz) of standard op-amp. The signal to noise ratio of the ultra low-power op-amp is 44 dB.

Citation Download Citation

Chuang Zhang, Ashok Srivastava, and Pratul Ajmera "Noise analysis of an 0.8-V ultra-low power CMOS operational amplifier", Proc. SPIE 5113, Noise in Devices and Circuits, (12 May 2003); https://doi.org/10.1117/12.488938

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