Dr. Chui-Fu Chiu Profile

Dr. Chui-Fu Chiu

at Nanya Technology Corp

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Author

Publications (8)

Proceedings Article | 5 April 2012 Paper

Toward faster and better litho control in high-volume manufacturing

Chui-Fu Chiu, Chun-Yen Huang, Wen-Bin Wu, Chiang-Lin Shih, Healthy Huang, James Manka, DongSub Choi, Arthur Lin, David Tien

Proceedings Volume 8324, 832426 (2012) https://doi.org/10.1117/12.916409

KEYWORDS: Overlay metrology, Semiconducting wafers, Scatterometry, Image segmentation, Metrology, Control systems, Lithography, Calibration, High volume manufacturing, Critical dimension metrology

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Proceedings Article | 5 April 2012 Paper

Impacts of overlay correction model and metrology sampling scheme on device yield

Chui-Fu Chiu, Chun-Yen Huang, Jason Shieh, Tsann-Bim Chiou, Albert Li, Chiang-Lin Shih, Alek Chen

Proceedings Volume 8324, 83241S (2012) https://doi.org/10.1117/12.916601

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Data modeling, Time metrology, Process modeling, Instrument modeling, Error analysis, Process control, Yield improvement

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Proceedings Article | 5 April 2012 Paper

Overlay control methodology comparison: field-by-field and high-order methods

Chun-Yen Huang, Chui-Fu Chiu, Wen-Bin Wu, Chiang-Lin Shih, Chin-Chou Kevin Huang, Healthy Huang, DongSub Choi, Bill Pierson, John Robinson

Proceedings Volume 8324, 832427 (2012) https://doi.org/10.1117/12.916427

KEYWORDS: Semiconducting wafers, Overlay metrology, Process control, Scanners, Lithography, Control systems, Metrology, Data modeling, Composites, Standards development

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Proceedings Article | 20 April 2011 Paper

Methodology for overlay mark selection

Chin-Chou Kevin Huang, Chao-Tien Healthy Huang, Anna Golotsvan, David Tien, Chui-Fu Chiu, Chun-Yen Huang, Wen-Bin Wu, Chiang-Lin Shih

Proceedings Volume 7971, 79712B (2011) https://doi.org/10.1117/12.879378

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Data modeling, Lithography, Scanners, Error analysis, Optical lithography, Etching, Lithographic illumination

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Proceedings Article | 20 April 2011 Paper

Automatic optimization of metrology sampling scheme for advanced process control

Chuei-Fu Chue, Chun-Yen Huang, Chiang-Lin Shih

Proceedings Volume 7971, 79711O (2011) https://doi.org/10.1117/12.879375

KEYWORDS: Metrology, Overlay metrology, Semiconducting wafers, Scanners, Process control, Manufacturing, Yield improvement, Data modeling, Control systems, Optimization (mathematics)

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Proceedings Article | 11 December 2009 Paper

Optimization of alignment/overlay sampling and marker layout to improve overlay performance for double patterning technology

Chuei-Fu Chue, Tsann-Bim Chiou, Chun-Yen Huang, Alek Chen, Chiang-Lin Shih

Proceedings Volume 7520, 75200G (2009) https://doi.org/10.1117/12.837137

KEYWORDS: Semiconducting wafers, Optical alignment, Overlay metrology, Statistical modeling, Metrology, Time metrology, Double patterning technology, Data modeling, Photomasks, Scanners

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Double patterning technology is capable of extending usability of immersion ArF systems for 32nm half-pitch node and below. However, overlay errors between the two patterning steps will directly contribute to critical dimension variation in a dual litho-etch process. The overlay errors need to be reduced significantly to meet the tight critical dimension uniformity requirement in the technology nodes. The present scanners are able to correct intra- and inter-field overlay errors that include not only linear terms but also certain higher-order terms. As a result, a 3nm overlay requirement for DPT becomes feasible by applying the most advanced correction schemes. Overlay modeling with a larger number of sample fields will give a more accurate estimate of the model parameters and will therefore improve the overlay corrections; however, metrology time will increase simultaneously. To balance the correction accuracy and metrology time, the number of fields and its layout on the wafer must be optimized. This also applies to wafer alignment, one of the other factors that determine the overlay performance. A bad alignment sampling scheme will cause a poor overlay performance in the end. Increasing the number of sample fields can improve the alignment performance but wafer throughput will be impacted immediately. Performance of the intra-field correction is dependent on number and distribution of the markers within an exposure field. Correction per field, for instance, is one of the most effective correction schemes. However, it needs to measure extra markers in each field for overlay modeling especially when including high-order terms. To limit the chip area occupied by the markers and the metrology time, it is necessary to well control the number of the markers. Moreover, accuracy of the overlay models is sensitive to layout of the markers. The overlay marker layout hence needs to be optimized to gain a robust correction with a minimum number of markers. In this paper, firstly we developed various geometry-based sampling methods for both alignment and overlay corrections to evaluate correction robustness while keeping the number of sample fields as small as possible. The results show that modeling with a limited number of fields can adequately describe a full-wafer alignment/overlay signature and the errors can be well corrected accordingly. A hybrid sampling approach was then proposed taking into consideration the spatial coverage (geometry-based) as well as the overlay signature of the fields. To improve the intra-field correction, an algorithm to assist in designing the layout of the overlay markers on a mask was developed. The most effective marker layouts with the least number of markers were suggested for different correction schemes. Using the most effective correction scheme as well as the proposed optimization techniques, the overlay performance can be improved to meet the overlay requirement of the 32nm DPT.

Proceedings Article | 23 March 2009 Paper

Using intrafield high-order correction to achieve overlay requirement beyond sub-40nm node

Chun Yen Huang, Chuei Fu Chue, An-Hsiung Liu, Wen Bin Wu, Chiang Lin Shih, Tsann-Bim Chiou, Juno Lee, Owen Chen, Alek Chen

Proceedings Volume 7272, 72720I (2009) https://doi.org/10.1117/12.813628

KEYWORDS: Semiconducting wafers, Overlay metrology, Optical alignment, Scanners, Time metrology, Metrology, Process control, Double patterning technology, Performance modeling, Reticles

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Proceedings Article | 27 March 2007 Paper

Verification of high-transmittance PSM with polarization at 193-nm high-NA system

Chui Fu Chiu, Chih Li Chen, Jenn Wei Lee, Wen Bin Wu, Chiang Lin Shih, Feng Yi Chen, Jeng Ping Lin

Proceedings Volume 6520, 65202E (2007) https://doi.org/10.1117/12.711893

KEYWORDS: Line edge roughness, Photomasks, Polarization, Nanoimprint lithography, Resolution enhancement technologies, Electroluminescence, Lithographic illumination, Phase shifts, Transmittance, Optical lithography

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Showing 5 of 8 publications

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