As 193 nm lithography appears to be a long term solution for wafer patterning, we expect new resolution enhancement coming from advanced mask technologies. We have studied an assembly technique that could increase mask capability towards advanced wafer patterning. This paper presents a proof of concept for the use of bonded mask, obtained with two plates assembled together. The initial application targeted here is an alternative solution to pellicle. A special process has been worked out to obtain bonded test samples. Based on the knowledge of silicon wafer bonding techniques, we have developed a process that allows bonding of fused silica square plates. Constant progress allowed us to use specific materials used in mask manufacturing, such as chromium and fused silica, and also specific square shapes and rather large thickness. The final demonstrator is a Chromium on Glass mask (COG), on which a hard pellicle has been bonded without any additional material. The pellicle was 0.5 mm thick and 100 mm in diameter. This test sample has been qualified in a 248 nm AIMS tool. We made comparative measurements on different occurrence of the same chip, covered or not covered by the pellicle. We have shown evidence of induced spherical aberration for conventional illumination and this has been confirmed by simulation. Image fidelity was proven for positive and negative features. Through focus image capture showed that process windows were not impacted by the hard pellicle.
During the last five years scatterometry measurement using ellispometry and reflectometry has met a great interest in nano and microelectronics fab. Today, this technology of measurement is used to control lot production and has become mature for 1D-grating measurements. Nevertheless, some aspects of this method of measurement are always under research studies. This paper focuses on one of these aspects: the evaluation of the influence of the "real-life 1D-structure" (linewidth variations along the lines and line to line, roughness, defect inside the grating) on spectroscopic signatures and on scatterometry measurement methods. The measurements have been carried out on KLA-TENCOR ellispometer and on Nanometrics reflectometer in order to compare the two methods of measurement. The simulations have been done with MMFE (Modal Method of Fourier Expansion) software developed by LETI labs. To control defect characteristics and defect distributions, one wafer was printed using electron beam lithography. The aim is the evaluation of the impact of defects in the grating on the spectroscopic signatures and its influence on extracted geometrical parameters by fitting the experimental curves. Different deviations to real-life structures have been studied. First we focus on the influence of typical defects of lithography processes such as bridging and partial destruction of lines and on the influence of CD distribution values inside the grating. Then, we study the influence and the possibilities of measuring Line Edge Roughness (LER). For LER measurements different targets have been also exposed on e-beam tool. Simulations and experimental measurements have been carried out. All the results obtained have been compared with imaging standard tool: top down SEM measurement.
This paper shows the capability of chromeless phase lithography (CPL) and is particularly focused on different strategies for optical proximity corrections (OPC). A chromeless phase database is easily obtained from the original layout by changing the chromium pattern into a phase pattern. However, a specific optical proximity correction has to be applied due to the phase effect and the high transmission of the mask. Mask Error Enhancement Factor (MEEF) and process window for CPL technology have been estimated through wafer exposures. Moreover, various optical proximity correction strategies have been explored through a comparison between phase and chromium features such as hammerhead, zebra and scattering bars 1,2. Indeed, depending on the density of the pattern, we can improve the contrast and the process window by changing the local transmission. The transmission can be controlled by the addition of sub resolution chromium feature such as zebra chromium transverse features on the line for dense pattern, or chromium scattering bars in the space for a sparse pattern, or chromium patches on the line end. From 65 nm node measurements and 45 nm node simulations, the authors will then present the most effective sub resolution pattern to implement.
The merits of complementary double dipole illumination using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is investigated. Off-axis dipole illumination shows a significant improvement in the resolution for lines and spaces oriented along the direction perpendicular to the dipole orientation. However, there is also a significant loss of resolution along the dipole direction. Consequently, two dimensional circuit patterning requires a double exposure to improve the resolution in both directions. Thus, the original layout must be decomposed into two masks: one containing the features to be primarily imaged with one dipole and another one with features to be imaged in the complementary direction. The horizontal and vertical lines must be selected and protective patches are required on each mask to protect the pattern formed by the complementary exposure. The potential capability of the dipole illumination used in conjunction with the immersion lithography for 45 nm and 32 nm nodes will be described. The Mentor Graphic approach based on the model assisted decomposition for the Double Dipole Lithography (DDL) was applied to the small clips of the 2D layout of the gate level for random logic. The lithographic process window and the CD control will be estimated through simulation.
This paper focuses on the capability of the spectroscopic scatterometry method to determine holes features parameters from experimental 3D-target. Scatterometry uses optical tools for spectra recording as ellipsometer form KLA TENCOR and a MMFE (Modal Method of Fourier Expansion) software tool including an advanced electromagnetic simulator and an optimization loop for data extraction.
This study reports on 3D-MMFE regression of different dense holes square and rectangular matrix structures on the simplest structure-resist on silicon-to extract diameter, height of the holes. The holes diameter is from 90nm to 500nm, and the duty ratio is from 1:1 to 2:2 (CD/Space). To be close to real production stack the same matrices have been studied on more complex stack (close to via level with different dielectric material: FSG, dense SiOC).
Finally this study is focused on an analysis on simulation and experiment of the relative sensitivity position of a hole inside the basic element of diffraction. That shows the possibility of scatterometry measurement in detecting via shift.
With the strong increase of mask complexity and associated price for each new technology node, mask less lithography represents more and more an interesting and complementary alternative for ASIC manufacturing especially in the fields of low volume and leading eadge technology applications. In the semiconductor business where prices and cycle time are constantly pressured, the capability and flexibility of the electron beam direct write offer an effective real cost and cycle time opportunity thanks to its high-resolution capability but also to its ability to print, modify or correct design everywhere in a circuit. This paper highlights application examples where the advantages of this lithography solution are demonstrated for advanced research and development application with the patterning of 45 nm SRAM and for the fast validation of architecture designs. This work confirms that mask less lithography can be transparently placed into production environment, in association with the "golden" optical lithography reference.
As we move technology further and further down the geometry scale we are coming upon imaging situations where our use of existing optical lithography is being questioned due to the lack of process margin in manufacturing lines. This is especially apparent in the imaging of contacts where memory devices, that generally have the densest arrays of these features, may no longer be able to print the desired features. To overcome this it is necessary to either modify the design, a very expensive and time consuming process, or find an imaging process capable of printing the desired features. Electron Projection Lithography (EPL) provides an option to print very small features with a large process margin.
In this paper we detail the performance of both memory and logic based designs in an EPL process. We detail the manufacture and results of stencil mask manufacture. Data is also presented showing the imaging results (DOF, exposure latitude, pattern transfer) of features down to 50nm imaged on Nikon’s EB1A tool.
KEYWORDS: Line width roughness, Electron beam direct write lithography, Semiconducting wafers, Electron beam lithography, Electron beams, Manufacturing, Etching, Photoresist processing, Coating, Semiconductors
Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments. Patterning for sub-45nm node technology requires the development of high performance processes. Different alternatives for the improvement of EBDW lithography are investigated in this paper for the ASIC manufacturing on 300mm wafer size. Among them, process development has been tuned for clear field equivalent level to improve both line width roughness by monitoring post applied bake conditions, and both process window by specific design correction. Concerning dark field level, process resolution has been improved by a shrinkage technique.
Spectroscopic scatterometry is an optical metrology technique based on light scattering aiming at measuring geometrical dimensions, such Critical Dimension (CD) but also height or depth, side-wall angle and even more tiny details in a line profile. Scatterometry tool measures and analyzes the spectrum scattered or diffracted from a periodic target patterned on a wafer. Scatterometry is strongly considered as an alternative or as a complementary technique to CDSEM for 90 nm and below technology nodes. Like other optical metrology techniques, scatterometry measurements are rapid, non-destructive and highly repeatable. Actual tools have been assessed for dense to semi-isolated lines CD metrology and profiling. Developments are now targeting hole measurement. 2D-scatterometry (scatterometry on 3D patterns) becomes mature and begins to be used in advanced fab for CD control after lithography. This paper focuses on the capability of the spectroscopic scatterometry method to determine holes features and to try to give theoretical limits of method. Scatterometry uses an optical tool for spectra recording and a software tool including an advanced electromagnetic simulator and an optimization loop for data extraction. The first part of this study reports on the influence of bi-periodic structures in the experimental analysis of holes measurements. Then a limitation in holes density is defined. The second part of this study is a theoretical analysis based on simulation of the sensitivity of scatterometry with respect to various holes parameters. Following parameters are generally taken into account: holes diameter, holes ellipticity (elliptical ratio), holes roundness, holes depth and tilt angle for non-circular holes. We determine the respective influence of these parameters on ellipsometric spectra.
Laurent Pain, M. Jurdit, Yves LaPlanche, J. Todeschini, Serdar Manakli, G. Bervin, Ramiro Palla, A. Beverina, R. Faure, X. Bossy, H. Leininger, S. Tourniol, M. Broekaart, F. Judong, K. Brosselin, P. Gouraud, Veronique De Jonghe, Daniel Henry, M. Woo, Peter Stolk, B. Tavel, F. Arnaud
The introduction of Electron Beam Direct Write lithography into production represents a
challenging alternative to reduce cost and cycle time increase induced by the introduction of new
generation nodes. This paper details the development work performed to insert transparently direct
write lithography process and alignment strategies into CMOS process flows. Finally, this
interchangeability between E-Beam and optical lithography steps offers a complete flexibility for
device architecture validation and allowed the development of a complete low cost 65nm platform
including low-power and general-purpose applications.
With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.
An easy way to pattern 65nm CD target, when optical lithography technology is not available, is to use an Electron Beam Direct Write tool (EBDW), which is well known for its high resolution patterning potentials, with the drawback of a very low throughput. Emerging techniques of electron projection lithography also propose the same patterning capability with enhanced throughput. One of the most crucial issues, when dealing with integration, is the overlay capability of the systems. This paper exposes the studies made on the overlay capability issue of the LEICA EBDW installed in STMicroelectronics (STM) production plant in Crolles (France) and proves our tool is ready to support the 65nm node technology development.
Using scatterometry based on Spectroscopic Ellipsometry, a complete study of Gate lithography level measurement on standard products has been conducted. Experiments were done on typical ST batches for 120, 90, and 65 nm nodes. KLA-Tencor SpectraCD SE system is used to collect and analyze line critical dimensions and profiles. A systematic correlation with Scanning Electron Microscope (SEM) is done, completed by a cross section analysis. The study also takes into account lithography defect anlysis using a specific targets with intentionally generated process failures. Our objective is to determine the sensitivity window of such measurment technique to process defect and marginal process conditions. We show that KLA-Tencor SpectraCD allows a full reconstruction of the line profile - as well as the film stack underneath it - with values that are in agreement with production control. Cpm values obtained on products demonstrate that SE based scatterometry fulfils all requirements to be integrated in a production envrionemnt and provides suitable metrology for advanced lithography process monitoring.
In this study, it is investigated how chemical modifications of a given resist platform can induce improvements in e-beam lithographic performances. Molecular weight (Mw) as well as photo-acid generator (PAG) modifications will act as fine tuners for Sumitomo NEB-33 negative resist to match specific applications: preparation of advanced CMOS R&D architecture (highly resolving resists needed) and fast patterning for production environment (highly sensitive resists needed).
For the sub-90 nm node integrated circuits design rules, ITRS forecasts require minimal gate line width down to 55-35 nm. To reach such aggressive targets, most advanced optical lithography tools combined with all reticle enhancement techniques will be requested inducing important manufacturing cost and mask cycle time increase. In order to address prototyping market and reduce fabrication cost, shaped electron beam lithography may represent a technological alternative for cost reduction due to its high resolution and potential throughput capabilities. This paper is focused on the integration of this technology in standard ASIC plant, including resist process and overlay capabilities.
Engine management optimization and waste exhaust-gas control require engine transients measurements. The infrared tunable diode laser absorption spectroscopy method can measure absolute molecule concentrations, gas temperature and pressure at high rate. The technique has been improved to measure NO or CO concentrations, as well as temperature and pressure of engine exhaust-gas. Measurements with a time resolution of one millisecond have been achieved in one of the cylinder exhaust pipe without any gas sampling.
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