In the past few decades, leading edge logic technology scaling has been the main driver for semiconductor metrology developments. As traditional device scaling is slowing down, the semiconductor industry is focusing also on heterogeneous integration approaches, which leverage advanced packaging technologies to integrate devices designed and manufactured separately using the most suitable process technology for each device. Heterogeneous integration presents significant metrology challenges, which are different from what is encountered at the logic device level in terms of materials and specifically dimensions. Large-scale 3D structures need to be characterized with unprecedented accuracies and advanced optical techniques play a pivotal role. In this paper, some metrology challenges in heterogeneous integration are introduced and discussed related to TSV characterization including depth and reveal height, wafer bonding measurements, and dimensional and overlay metrology for processing leading to bump receivers and bump formation. Current capabilities utilizing various imaging and interferometry techniques are presented and their limitations discussed.
3-dimensional chiplet device architectures are expected to provide improved device performance, efficiency, and footprint beyond what is capable with 2-dimensional scaling technologies. Thick resist lithography of damascene and plating resists, as well as organic dielectric materials, plays a critical role in chiplet integration. However, thick resist lithography requires viscous resist solutions, specialized tooling, and long processing times. This makes patterning using these resists inherently prone to uniformity issues, which has become a crucial issue for scaling. This work highlights two strategic areas of thick resist patterning development: improved resist coating methods; and enhanced focus control during exposure. Herein, we show a track-based method for carefully controlled uniformity of the resist coating thickness, with some sacrifice of through-put. In addition, we show stepper-based focus methods to account for die level variations in resist and wafer thickness, as well as local topography. Combined, these provide precise cross-wafer control of thick resist dimensions.
Comprehensive through-silicon-via (TSV) characterization, including grind side measurements, is critical to ensure device reliability in chiplet technology. Here we report on TSV metrology using spectral interferometry (SI), which is used to acquire absolute phase information of polarized and broad-band light interacting with a sample. This phase information can be translated into the optical path length of the partial beams traveling within the structure. We utilize the spatial separation of peaks related to light reflected from the top surface and the surface of interest to directly measure the TSV depth after reactive ion etching as well as the reveal height on the grind side, without modeling and even in the presence of multilayers or surrounding patterning. Polarization-dependent SI measurements enable the quantification of asymmetry at the bottom of the TSVs not visible in top-down CD measurements. SI is robust and fast and unveils novel information in TSV metrology not accessible with established in-line metrology techniques.
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